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INTEGRATED CIRCUITS
DATA SHEET
SAA7108AE; SAA7109AE HD-CODEC
Product specification Supersedes data of 2003 Mar 26 2004 Jun 29
Philips Semiconductors
Product specification
HD-CODEC
CONTENTS 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 9 9.1 9.2 9.3 9.4 9.5 9.6 FEATURES Video decoder Video scaler Video encoder Common features APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAMS PINNING FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO ENCODER PART Reset conditions Input formatter RGB LUT Cursor insertion RGB Y-CB-CR matrix Horizontal scaler Vertical scaler and anti-flicker filter FIFO Border generator Oscillator and Discrete Time Oscillator (DTO) Low-pass Clock Generation Circuit (CGC) Encoder RGB processor Triple DAC HD data path Timing generator Pattern generator for HD sync pulses I2C-bus interface Power-down modes Programming the graphics acquisition scaler of the video encoder Input levels and formats FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO DECODER PART Decoder Decoder output formatter Scaler VBI data decoder and capture (subaddresses 40H to 7FH) Image port output formatter (subaddresses 84H to 87H) Audio clock generation (subaddresses 30H to 3FH) 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 11 11.1 11.2 12 13 14 15 16 16.1 16.2 17 17.1 17.2 17.3 18 18.1 18.2 19 19.1 19.2 19.3 19.4 20 21 22 23 24 25
SAA7108AE; SAA7109AE
INPUT/OUTPUT INTERFACES AND PORTS OF DIGITAL VIDEO DECODER PART Analog terminals Audio clock signals Clock and real-time synchronization signals Video expansion port (X port) Image port (I port) Host port for 16-bit extension of video data I/O (H port) Basic input and output timing diagrams for the I and X ports BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS OF THE DIGITAL VIDEO ENCODER PART CHARACTERISTICS OF THE DIGITAL VIDEO DECODER PART TIMING Digital video encoder part Digital video decoder part APPLICATION INFORMATION Reconstruction filter Analog output voltages Suggestions for a board layout I2C-BUS DESCRIPTION Digital video encoder part Digital video decoder part PROGRAMMING START SET-UP OF DIGITAL VIDEO DECODER PART Decoder part Audio clock generation part Data slicer and data type control part Scaler and interfaces PACKAGE OUTLINE SOLDERING DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2004 Jun 29
2
Philips Semiconductors
Product specification
HD-CODEC
1 1.1 FEATURES Video decoder
SAA7108AE; SAA7109AE
* Six analog inputs, internal analog source selectors, e.g. 6 x CVBS or (2 x Y/C and 2 x CVBS) or (1 x Y/C and 4 x CVBS) * Two analog preprocessing channels in differential CMOS style for best S/N performance * Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel * Switchable white peak control * Two built-in analog anti-aliasing filters * Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or Y/C signals are available on the Image Port Data (IPD) port under I2C-bus control * On-chip clock generator * Line-locked system clock frequencies * Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection * Requires only one crystal (either 24.576 MHz or 32.11 MHz) for all standards * Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards * Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM * User programmable luminance peaking or aperture correction * Cross-colour reduction for NTSC by chrominance comb filtering * PAL delay line for correcting PAL phase errors * Brightness Contrast Saturation (BCS) and hue control on-chip * Two multi functional real-time output pins controlled by the I2C-bus * Multi-standard VBI data slicer decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), Closed Caption (CC), Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE) etc. * Standard ITU 656 Y-CB-CR 4 : 2 : 2 format (8-bit) on IPD output bus
(1) MacrovisionTM is a trademark of the Macrovision Corporation.
* Enhanced ITU 656 output format on IPD output bus containing: - active video - raw CVBS data for INTERCAST applications (27 MHz data rate) - decoded VBI data * Detection of copy protected input signals according to the MacrovisionTM(1) standard. Can be used to prevent unauthorized recording of pay-TV or video tape signals. 1.2 Video scaler
* Both up and downscaling * Conversion to square pixel format * NTSC to 288 lines (video phone) * Phase accuracy better than 1/64 pixel or line, horizontally or vertically * Independent scaling definitions for odd and even fields * Anti-alias filter for horizontal scaling * Provides output as: - scaled active video - raw CVBS data for INTERCAST, WAVE-PHORE, POPCON applications or general VBI data decoding (27 MHz or sample rate converted) * Local video output for Y-CB-CR 4 : 2 : 2 format (VMI, VIP, ZV).
2004 Jun 29
3
Philips Semiconductors
Product specification
HD-CODEC
1.3 Video encoder
SAA7108AE; SAA7109AE
* Adjustable output levels for the DACs * Programmable horizontal and vertical input synchronization phase * Programmable horizontal sync output phase * Internal Colour Bar Generator (CBG) * Optional support of various Vertical Blanking Interval (VBI) data insertion * Macrovision Pay-per-View copy protection system rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; this applies to SAA7108AE only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information. 1.4 Common features
* Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from a PC * Supports Intel(R) Digital Video Out (DVO) low voltage interfacing to graphics controller * 27 MHz crystal-stable subcarrier generation * Maximum graphics pixel clock 85 MHz at double edged clocking, synthesized on-chip or from external source * Programmable assignment of clock edge to bytes (in double edged mode) * Synthesizable pixel clock (PIXCLK) with minimized output jitter, can be used as reference clock for the VGC, as well * PIXCLK output and bi-phase PIXCLK input (VGC clock loop-through possible) * Hot-plug detection through dedicated interrupt pin * Supported VGA resolutions for PAL or NTSC legacy video output up to 1280 x 1024 graphics data at 60 or 50 Hz frame rate * Supported VGA resolutions for HDTV output up to 1920 x 1080 interlaced graphics data at 60 or 50 Hz frame rate * Three Digital-to-Analog Converters (DACs) for CVBS (BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR) at 27 MHz sample rate (signals in parenthesis are optionally selected), all at 10-bit resolution * Non-interlaced CB-Y-CR or RGB input at maximum 4 : 4 : 4 sampling * Downscaling and upscaling from 50 to 400 % * Optional interlaced CB-Y-CR input of Digital Versatile Disk (DVD) signals * Optional non-interlaced RGB output to drive second VGA monitor (bypass mode, maximum 85 MHz) * 3 x 256 bytes RGB Look-Up Table (LUT) * Support for hardware cursor * HDTV up to 1920 x 1080 interlaced and 1280 x 720 progressive, including 3-level sync pulses * Programmable border colour of underscan area * Programmable 5 line anti-flicker filter * On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal) * Fast I2C-bus control port (400 kHz) * Encoder can be master or slave
* 5 V tolerant digital I/O ports * I2C-bus controlled (full read-back ability by an external controller, bit rate up to 400 kbits/s) * Versatile power-save modes * Boundary scan test circuit complies with the "IEEE Std. 1149.b1-1994" (separate ID codes for decoder and encoder) * Monolithic CMOS 3.3 V device * BGA156 package * Moisture Sensitive Level (MSL): e3. 2 APPLICATIONS
* Notebook (low-power consumption) * PCMCIA card application * AGP based graphics cards * PC editing * Image processing * Video phone applications * INTERCAST and PC teletext applications * Security applications * Hybrid satellite set-top boxes.
2004 Jun 29
4
Philips Semiconductors
Product specification
HD-CODEC
3 GENERAL DESCRIPTION
SAA7108AE; SAA7109AE
All inputs intended to interface to the host graphics controller are designed for low-voltage signals down to 1.1 V and up to 3.45 V. The video decoder, a 9-bit video input processor, is a combination of a 2-channel analog pre-processing circuit including source selection, anti-aliasing filter and Analog-to-Digital Converter (ADC), automatic clamp and gain control, a Clock Generation Circuit (CGC), and a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM). The decoder includes a brightness, contrast and saturation control circuit, a multi-standard VBI data slicer and a 27 MHz VBI data bypass. The pure 3.3 V (5 V compatible) CMOS circuit SAA7108AE; SAA7109AE, consisting of an analog front-end and digital video decoder, a digital video encoder and analog back-end, is a highly integrated circuit especially designed for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU-R BT.601 compatible colour component values. The encoder can operate fully independently at its own variable pixel clock, transporting graphics input data, and at the line-locked, single crystal-stable video encoding clock. As an option, it is possible to slave the video PAL/NTSC encoding to the video decoder clock with the encoder FIFO acting as a buffer to decouple the line-locked decoder clock from the crystal-stable encoder clock.
The SAA7108AE; SAA7109AE is a new multi-standard video decoder and encoder chip, offering high quality video input and TV output processing as required by PC-99 specifications. It enables hardware manufacturers to implement versatile video functions on a significantly reduced printed-circuit board area at very competitive costs. Separate pins for supply voltages as well as for I2C-bus control and boundary scan test have been provided for the video encoder and decoder sections to ensure both flexible handling and optimized noise behaviour. The video encoder is used to encode PC graphics data at maximum 1280 x 1024 resolution (optionally 1920 x 1080 interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and anti-flicker filter (maximum 5 lines) ensures properly sized and flicker-free TV display as CVBS or S-video output. Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals together with a TTL composite sync to feed SCART connectors. When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor at maximum 1280 x 1024 resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this port can provide Y, PB and PR signals for HDTV monitors. The encoder section includes a sync/clock generator and on-chip DACs.
4
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME BGA156 DESCRIPTION plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm VERSION SOT472-1
SAA7108AE SAA7109AE
2004 Jun 29
5
Philips Semiconductors
Product specification
HD-CODEC
5 QUICK REFERENCE DATA SYMBOL VDDD VDDA Tamb PA+D Note PARAMETER digital supply voltage analog supply voltage ambient temperature analog and digital power dissipation note 1
SAA7108AE; SAA7109AE
CONDITIONS
MIN. 3.15 3.15 0 -
TYP. 3.3 3.3 - -
MAX. 3.45 3.45 70 1.7
UNIT V V C W
1. Power dissipation is extremely dependent on programming and selected application. 6 BLOCK DIAGRAMS
handbook, full pagewidth
digital video input and output X port
analog video input
CVBS, Y/C
ANALOG VIDEO ACQUISITION AND DEMODULATOR
SCALER
I port (IPD)
digital video output
VIDEO DECODER PART VIDEO ENCODER PART digital video Y-CB-CR/RGB graphics input PD SCALER AND INTERLACER VIDEO ENCODER CVBS, Y/C RGB analog video output
MHB903
Fig.1 Simplified block diagram.
2004 Jun 29
6
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PD11 to PD0 C1, C2, B1, B2, A2, B4, B3, A3, F3, H1, H2, H3 INPUT FORMATTER FIFO AND UPSAMPLING LUT AND CURSOR RGB TO Y-CB-CR MATRIX DECIMATOR 4 : 4 : 4 to 4 : 2 : 2 PIXCLKI F2 C6 FIFO BORDER GENERATOR VIDEO ENCODER HD OUTPUT TRIPLE DAC C7 C8 HORIZONTAL SCALER VERTICAL SCALER VERTICAL FILTER BLUE_CB_CVBS GREEN_VBS_CVBS RED_CR_C_CVBS
Philips Semiconductors
HD-CODEC
Fig.2 Block diagram (video encoder part).
andbook, full pagewidth
7
SAA7108AE SAA7109AE
G4 PIXEL CLOCK SYNTHESIZER CRYSTAL OSCILLATOR A5 XTALIe XTALOe TTX_SRES 27 MHz VSVGC CBO HSVGC SDAe SCLe RESe A6 C3 TIMING GENERATOR G1 F1 G3 E3 C4 I2C-BUS CONTROL G2 E2 D2 PIXCLKO FSVGC TTXRQ_XCLKO2
D7 D8 F12
VSM HSM_CSYNC TVD
SAA7108AE; SAA7109AE
MBL785
Product specification
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k, full pagewidth
AI12 AI21 AI22
P10 P9 P7 P6 M10 P12 P8 N10 ANALOG DUAL ADC
AI23 AI24 AOUT AI1D AI2D AGND
DIGITAL DECODER WITH ADAPTIVE COMB FILTER
EVENT CONTROLLER
IMAGE PORT PIN MAPPING
2004 Jun 29
LLC2 LLC RTS0
(1)
Philips Semiconductors
HD-CODEC
XCLK
XPD [7:0]
XRV XRH
XTRI HPD [7:0] K1 SDAd SCLd L12 M11
TEST5
TEST3
TEST1 TEST0
RTCO
RTS1
XDQ
XRDY
TEST4 J2 J1
TEST2 J3
M14 L14 L13 K13 L10 M3 M4
N2 L5 N3 K2, K3, L1 to L3 M1, M2, N1
A13, D12, C12, B12, A12, C11, B11, A11 I/O CONTROL
C10 B10 H13
REAL-TIME OUTPUT RESd CE XTOUTd XTALId XTALOd AI11 M12 N14 P4 P2 P3 P13 P11 CLOCK GENERATION AND POWER-ON CONTROL
EXPANSION PORT PIN MAPPING
I2C-BUS
X PORT I/O FORMATTING
chrominance of 16-bit input
PROGRAMMING REGISTER ARRAY
A/B REGISTER MUX
SAA7108AE SAA7109AE
E14, D14, C14, B14, E13, D13, C13, B13 H14 G12 F13 F14 G13
IPD [7:0] IDQ IGPH IGPV IGP0 IGP1
FIR-PREFILTER HORIZONTAL LINE VERTICAL PRESCALER FINE FIFO SCALING AND (PHASE) BUFFER SCALER BCS SCALING
8
VIDEO FIFO
BOUNDARY SCAN TEST
AUDIO CLOCK GENERATION
GENERAL PURPOSE VBI DATA SLICER
TEXT FIFO
32 to 8(16) MUX
H12
ICLK
J14 M7, D11, F11, D10, G11, M8, M9, E11, K4, H4, H11, N7 to N9, J4, J11, N11 L6, M13 N12, N13 K11 L7, L9 P5 L4, L11 VDDId VDDEd VDDAd VSSId VSSEd VSSAd VIDEO/TEXT ARBITER G14
ITRDY ITRI
SAA7108AE; SAA7109AE
N4 M6 M5 N6 N5 TCLKd TDId
K12 J13 K14 J12 ASCLK
L8
MBL791
AMCLK
VDDXd
TRSTd TMSd TDOd
ALRCLK AMXCLK
(1)
VSSXd
Product specification
(1) The pins RTCO and ALRCLK are used for configuration of the I2C-bus interface and the definition of the crystal oscillator frequency at RESET (pin strapping).
Fig.3 Block diagram (video decoder part).
Philips Semiconductors
Product specification
HD-CODEC
7 PINNING SYMBOL PD7 PD4 TRSTe XTALIe XTALOe DUMP VSSXe RSET VDDAe HPD0 HPD3 HPD7 PD9 PD8 PD5 PD6 TDIe VDDAe DUMP VSSAe VDDAe TEST1 HPD1 HPD4 IPD0 IPD4 PD11 PD10 TTX_SRES TTXRQ_XCLKO2 VSSIe BLUE_CB_CVBS 2004 Jun 29 PIN A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 TYPE(1) I I I/pu I O O S O S I/O I/O I/O I I I I I/pu S O S S I I/O I/O O O I I I O S O
SAA7108AE; SAA7109AE
DESCRIPTION MSB of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment MSB - 3 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment test reset input for Boundary Scan Test (BST) (encoder); active LOW; with internal pull-up; notes 2 and 3 27 MHz crystal input (encoder) 27 MHz crystal output (encoder) DAC reference pin (encoder), 12 resistor connected to VSSAe ground for oscillator (encoder) DAC reference pin (encoder), 1 k resistor connected to VSSAe 3.3 V analog supply voltage (encoder) MSB - 7 of Host Port Data (HPD) output bus MSB - 4 of HPD output bus MSB of HPD output bus see Tables 9, 14 and 15 for pin assignment with different encoder input formats see Tables 9, 14 and 15 for pin assignment with different encoder input formats MSB - 2 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment MSB - 1 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment test data input for BST (encoder); note 4 3.3 V analog supply voltage (encoder) DAC reference pin (encoder); connected to A7 analog ground (encoder) 3.3 V analog supply voltage (encoder) scan test input 1, do not connect MSB - 6 of HPD output bus MSB - 3 of HPD output bus MSB - 7 of IPD output bus MSB - 3 of Image Port Data (IPD) output bus see Tables 9, 14 and 15 for pin assignment with different encoder input formats see Tables 9, 14 and 15 for pin assignment with different encoder input formats teletext input or sync reset input (encoder) teletext request output or 13.5 MHz clock output of the crystal oscillator (encoder) digital ground core (encoder) BLUE or CB or CVBS output 9
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL GREEN_VBS_CVBS RED_CR_C_CVBS VDDAe TEST2 HPD2 HPD5 IPD1 IPD5 TDOe RESe TMSe VDDIEe VSSIe VDDXe VSM HSM_CSYNC VDDAe VDDEd VDDId HPD6 IPD2 IPD6 TCKe SCLe HSVGC VSSEe VSSId n.c. IPD3 IPD7 VSVGC PIXCLKI PD3 VDD(DVO) VDDId TVD IGPV IGP0
PIN C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E11 E12 E13 E14 F1 F2 F3 F4 F11 F12 F13 F14
TYPE(1) O O S I I/O I/O O O O I I/pu S S S O O S S S I/O O O I/pu I I/O S S - O O I/O I I S S O O O
DESCRIPTION GREEN or VBS or CVBS output RED or CR or C or CVBS output 3.3 V analog supply voltage (encoder) scan test input 2, do not connect MSB - 5 of HPD output bus MSB - 2 of HPD output bus MSB - 6 of IPD output bus MSB - 2 of IPD output bus test data output for BST (encoder); note 4 reset input (encoder); active LOW test mode select input for BST (encoder); note 4 3.3 V digital supply voltage for core and peripheral cells (encoder) digital ground core (encoder) 3.3 V supply voltage for oscillator (encoder) vertical synchronization output to VGA monitor (non-interlaced) horizontal synchronization output to VGA monitor (non-interlaced) or composite sync for RGB-SCART 3.3 V analog supply voltage (encoder) 3.3 V digital supply voltage for peripheral cells (decoder) 3.3 V digital supply voltage for core (decoder) MSB - 1 of HPD output bus MSB - 5 of IPD output bus MSB - 1 of IPD output bus test clock input for BST (encoder); note 4 I2C-bus serial clock input (encoder) horizontal synchronization output to Video Graphics Controller (VGC) (optional input) digital ground peripheral cells (encoder) digital ground core (decoder) not connected MSB - 4 of IPD output bus MSB of IPD output bus vertical synchronization output to VGC (optional input) pixel clock input (looped through) MSB - 4 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment digital supply voltage for DVO cells 3.3 V digital supply voltage for core (decoder) TV Detector; hot-plug interrupt pin, HIGH if TV is connected multi-purpose vertical reference output with IPD output bus general purpose output signal 0 with IPD output bus
2004 Jun 29
10
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL FSVGC SDAe CBO PIXCLKO VDDEd IGPH IGP1 ITRI PD2 PD1 PD0 VSSEd VSSEd ICLK TEST0 IDQ TEST4 TEST5 TEST3 VDDId VDDId AMXCLK ALRCLK
PIN G1 G2 G3 G4 G11 G12 G13 G14 H1 H2 H3 H4 H11 H12 H13 H14 J1 J2 J3 J4 J11 J12 J13
TYPE(1) I/O I/O O O S O O I/(O) I I I S S I/O O O O I I S S I (I/)O
DESCRIPTION frame synchronization output to VGC (optional input) I2C-bus serial data input/output (encoder) composite blanking output to VGC; active LOW pixel clock output to VGC 3.3 V digital supply voltage for peripheral cells (decoder) multi-purpose horizontal reference output with IPD output bus general purpose output signal 1 with IPD output bus programmable control signals for IPD output bus MSB - 5 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment MSB - 6 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment MSB - 7 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment digital ground for peripheral cells (decoder) digital ground for peripheral cells (decoder) clock for IPD output bus (optional clock input) scan test output, do not connect data qualifier for IPD output bus scan test output, do not connect scan test input, do not connect scan test input, do not connect 3.3 V digital supply voltage for core (decoder) 3.3 V digital supply voltage for core (decoder) audio master external clock input audio left/right clock output; can be strapped to supply via a 3.3 k resistor to indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down) has been replaced by a 32.110 MHz crystal (ALRCLK = 1); notes 5 and 6 target ready input for IPD output bus control signal for all X port pins MSB of XPD bus MSB - 1 of XPD bus digital ground core (decoder) digital ground core (decoder) audio master clock output, must be less than 50 % of crystal clock real-time status or sync information line 0 audio serial clock output MSB - 2 of XPD bus MSB - 3 of XPD bus MSB - 4 of XPD bus 3.3 V digital supply voltage for core (decoder) vertical reference for XPD bus 11
ITRDY XTRI XPD7 XPD6 VSSId VSSId AMCLK RTS0 ASCLK XPD5 XPD4 XPD3 VDDId XRV 2004 Jun 29
J14 K1 K2 K3 K4 K11 K12 K13 K14 L1 L2 L3 L4 L5
I I I/O I/O S S O O O I/O I/O I/O S I/O
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL VSSEd VDDEd VDDXd VDDEd RTS1 VDDId SDAd RTCO
PIN L6 L7 L8 L9 L10 L11 L12 L13
TYPE(1) S S S S O S I/O (I/)O
DESCRIPTION digital ground for peripheral cells (decoder) 3.3 V digital supply voltage for peripheral cells (decoder) 3.3 V supply voltage for oscillator (decoder) 3.3 V digital supply voltage for peripheral cells (decoder) real-time status or sync information line 1 3.3 V digital supply voltage for core (decoder) I2C-bus serial data input/output (decoder) real-time control output; contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see external document "RTC Functional Description", available on request); the RTCO pin is enabled via I2C-bus bit RTCE; see notes 5 and 7 and Table 150 line-locked 12 clock output (13.5 MHz nominal) MSB - 5 of XPD bus MSB - 6 of XPD bus clock for XPD bus data qualifier for XPD bus test mode select input for BST (decoder); note 4 test clock input for BST (decoder); note 4 analog ground (decoder) 3.3 V analog supply voltage (decoder) 3.3 V analog supply voltage (decoder) analog test output (do not connect) I2C-bus serial clock input (decoder) reset output signal; active LOW (decoder) digital ground for peripheral cells (decoder) line-locked clock output (27 MHz nominal) MSB - 7 of XPD bus horizontal reference for XPD bus data input ready for XPD bus test reset input for BST (decoder); active LOW; with internal pull-up; notes 2 and 3 test data output for BST (decoder); note 4 test data input for BST (decoder); note 4 analog ground (decoder) analog ground (decoder) analog ground (decoder) analog ground (decoder) connected to substrate 3.3 V analog supply voltage (decoder) analog ground (decoder) analog ground (decoder) chip enable or reset input (with internal pull-up) 12
LLC2 XPD2 XPD1 XCLK XDQ TMSd TCKd VSSAd VDDAd VDDAd AOUT SCLd RESd VSSEd LLC XPD0 XRH XRDY TRSTd TDOd TDId VSSAd VSSAd VSSAd AGND VDDAd VSSAd VSSAd CE 2004 Jun 29
L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14
O I/O I/O I/O I/O I/pu I/pu S S S O I O S O I/O I/O O I/pu O I/pu S S S S S S S I
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL XTALId XTALOd XTOUTd VSSXd AI24 AI23 AI2D AI22 AI21 AI12 AI1D AI11 Notes
PIN P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13
TYPE(1) I O O S I I I I I I I I
DESCRIPTION 27 MHz crystal input (decoder) 27 MHz crystal output (decoder) crystal oscillator output signal (decoder); auxiliary signal ground for crystal oscillator (decoder) analog input 24 analog input 23 differential analog input for channel 2; connect to ground via a capacitor analog input 22 analog input 21 analog input 12 differential analog input for channel 1; connect to ground via a capacitor analog input 11
1. Pin type: I = input, O = output, S = supply, pu = pull-up. 2. For board design without boundary scan implementation connect TRSTe and TRSTd to ground. 3. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRSTe and TRSTd can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once. 4. In accordance with the "IEEE1149.1" standard the pads TDIe (TDId), TMSe (TMSd), TCKe (TCKd) and TRSTe (TRSTd) are input pads with an internal pull-up resistor and TDOe (TDOd) is a 3-state output pad. 5. Pin strapping is done by connecting the pin to supply via a 3.3 k resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down). 6. Pin ALRCLK: 0 = 24.576 MHz crystal (default); 1 = 32.110 MHz crystal. 7. Pin RTCO: operates as I2C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave address 40H/41H.
handbook, halfpage
MBL788
P N M L K J H G F E D C B A
SAA7108AE SAA7109AE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Fig.4 Pin configuration.
2004 Jun 29
13
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 1 1 A B C PD9 PD11 Pin assignment (top view) 2004 Jun 29 14 Philips Semiconductors
HD-CODEC
2 PD7 PD8 PD10
3 PD4 PD5 TTX_ SRES TMSe HSVGC PD3 CBO PD0 TEST3 XPD6 XPD3 XCLK XRDY
4 TRSTe PD6 TTXRQ_ XCLKO2 VDDIEe VSSEe VDD(DVO) PIXCLKO VSSEd VDDId VSSId VDDId XDQ TRSTd
5 XTALIe TDIe VSSIe
6 XTALOe VDDAe
7 DUMP DUMP
8 VSSXe VSSAe
9
10
11
12 HPD3 HPD4 HPD5
13 HPD7 IPD0 IPD1
14
RSET VDDAe HPD0 VDDAe TEST1 HPD1
IPD4 IPD5
BLUE_ GREEN_ RED_CR_C_ VDDAe TEST2 HPD2 CB_CVBS VBS_CVBS CVBS VDDXe VSM HSM_CSYNC VDDAe VDDEd VDDId VSSId VDDId VDDEd VSSEd
D E
TDOe TCKe
RESe SCLe
VSSIe
HPD6 n.c. TVD IGPH ICLK
IPD2 IPD3 IGPV IGP1 TEST0
IPD6 IPD7 IGP0 ITRI IDQ
F VSVGC PIXCLKI G FSVGC H J K L M N P PD2 TEST4 XTRI XPD5 XPD2 XPD0 SDAe PD1 TEST5 XPD7 XPD4 XPD1 XRH
VDDId AMXCLK ALRCLK ITRDY VSSId XRV TMSd TDOd VSSXd VSSEd TCKd TDId AI24 VDDEd VSSAd VSSAd AI23 VDDXd VDDAd VSSAd AI2D VDDEd RTS1 VDDId AMCLK SDAd RESd VSSAd AI1D RTS0 RTCO VSSEd VSSAd AI11 ASCLK LLC2 LLC CE
SAA7108AE; SAA7109AE
VDDAd AOUT SCLd VSSAd AGND VDDAd AI22 AI21 AI12
Product specification
XTALId XTALOd XTOUTd
Philips Semiconductors
Product specification
HD-CODEC
8 FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO ENCODER PART
SAA7108AE; SAA7109AE
For ease of analog post filtering the signals are twice oversampled to 27 MHz before digital-to-analog conversion. The total filter transfer characteristics (scaler and anti-flicker filter are not taken into account) are illustrated in Figs 5 to 10. All three DACs are realized with full 10-bit resolution. The CR-Y-CB to RGB dematrix can be bypassed (optionally) in order to provide the upsampled CR-Y-CB input signals. The 8-bit multiplexed CB-Y-CR formats are "ITU-R BT.656" (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in slave mode. For assignment of the input data to the rising or falling clock edge see Tables 9 to 15. In order to display interlaced RGB signals through a euro-connector TV set, a separate digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing of a TV set. The SAA7108AE; SAA7109AE synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock. It is also possible to connect pin RTCO of the decoder section to pin RTCI of the encoder section. Thus, information containing actual subcarrier frequency, PAL-ID etc. is available in case the line-locked clock of the decoder section is used for re-encoding of the encoder section. Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using a 50 Hz field rate. VPS data for program dependent automatic start and stop of such featured VCRs is loadable via the I2C-bus. The IC also contains Closed Caption and extended data services encoding (line 21), and supports teletext insertion for the appropriate bit stream format at a 27 MHz clock rate (see Fig.51). It is also possible to load data for the copy generation management system into line 20 of every field (525/60 line counting). A number of possibilities are provided for setting different video parameters such as: * Black and blanking level control * Colour subcarrier frequency * Variable burst amplitude etc.
The digital video encoder encodes digital luminance and colour difference signals (CB-Y-CR) or digital RGB signals into analog CVBS, S-video and, optionally, RGB or CR-Y-CB signals. NTSC M, PAL B/G and sub-standards are supported. The SAA7108AE; SAA7109AE can be directly connected to a PC video graphics controller with a maximum resolution of 1280 x 1024 (progressive) or 1920 x 1080 (interlaced) at a 50 or 60 Hz frame rate. A programmable scaler scales the computer graphics picture so that it will fit into a standard TV screen with an adjustable underscan area. Non-interlaced-to-interlaced conversion is optimized with an adjustable anti-flicker filter for a flicker-free display at a very high sharpness. Besides the most common 16-bit 4 : 2 : 2 CB-Y-CR input format (using 8 pins with double edge clocking), other CB-Y-CR and RGB formats are also supported; see Tables 9 to 15. A complete 3 x 256 bytes Look-Up Table (LUT), which can be used, for example, as a separate gamma corrector, is located in the RGB domain; it can be loaded either through the video input port PD (Pixel Data) or via the I2C-bus. The SAA7108AE; SAA7109AE supports a 32 x 32 x 2-bit hardware cursor, the pattern of which can also be loaded through the video input port or via the I2C-bus. It is also possible to encode interlaced 4 : 2 : 2 video signals such as PC-DVD; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed. Besides the applications for video output, the SAA7108AE; SAA7109AE can also be used for generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed to the DACs. This may be of interest for example, when the graphics controller provides a second graphics window at its video output port. The basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals at a crystal-stable clock rate of 13.5 MHz (independent of the actual pixel clock used at the input side), corresponding to an internal 4 : 2 : 2 bandwidth in the luminance/colour difference domain. Luminance and chrominance signals are filtered in accordance with the standard requirements of "RS-170-A" and "ITU-R BT.470-3".
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth 6
MBE737
Gv
(dB)
0 -6
-12 -18 -24
(1) (2)
-30 -36 -42 -48 -54 0 (1) SCBW = 1. (2) SCBW = 0. 2 4 6 8 10 12 f (MHz) 14
Fig.5 Chrominance transfer characteristic 1.
handbook, halfpage
2
MBE735
Gv (dB) 0
(1)
(2)
-2
-4
-6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1. (2) SCBW = 0.
Fig.6 Chrominance transfer characteristic 2.
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
Gv handbook, full pagewidth (dB) 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
(4) (2) (3) (1)
6
MGD672
(1) (2) (3) (4)
CCRS1 = 0; CCRS0 = 1. CCRS1 = 1; CCRS0 = 0. CCRS1 = 1; CCRS0 = 1. CCRS1 = 0; CCRS0 = 0.
Fig.7 Luminance transfer characteristic 1 (excluding scaler).
handbook, halfpage
MBE736
1
Gv (dB) 0
(1)
-1 -2
-3 -4 -5
0
2
4
f (MHz)
6
(1) CCRS1 = 0; CCRS0 = 0.
Fig.8 Luminance transfer characteristic 2 (excluding scaler).
2004 Jun 29
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth
Gv 6 0
MGB708
(dB)
-6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
Fig.9 Luminance transfer characteristic in RGB (excluding scaler).
handbook, full pagewidth
Gv 6 0
MGB706
(dB)
-6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
Fig.10 Colour difference transfer characteristic in RGB (excluding scaler).
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Philips Semiconductors
Product specification
HD-CODEC
8.1 Reset conditions
SAA7108AE; SAA7109AE
If Y-CB-CR is being applied as a 27 Mbyte/s data stream, the output of the input formatter can be used directly to feed the video encoder block. The horizontal upscaling is supported via the input formatter. According to the programming of the pixel clock dividers (see Section 8.10), it will upsample the data stream to 1 x, 2 x or 4 x the input data rate. An optional interpolation filter is available. The clock domain transition is handled by a 4 entries wide FIFO which gets initialized every field or explicitly at request. A bypass for the FIFO is available, especially for high input data rates. 8.3 RGB LUT
To activate the reset a pulse at least of 2 crystal clocks duration is required. During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC, CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set to 3-state. A reset also forces the I2C-bus interface to abort any running bus transfer and sets it into receive condition. After reset, the state of the I/Os and other functions is defined by the strapping pins until an I2C-bus access redefines the corresponding registers; see Table 2. Table 2 Strapping pins PIN FSVGC (pin G1) TIED LOW PRESET NTSC M encoding, PIXCLK fits to 640 x 480 graphics input
The three 256-byte RAMs of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the event that the indexed colour data is applied, the RAMs are addressed in parallel. The LUTs can either be loaded by an I2C-bus write access or can be part of the pixel data input through the PD port. In the latter case, 256 x 3 bytes for the R, G and B LUT are expected at the beginning of the input video line, two lines before the line that has been defined as first active line, until the middle of the line immediately preceding the first active line. The first 3 bytes represent the first RGB LUT data, and so on. 8.4 Cursor insertion
HIGH PAL B/G encoding, PIXCLK fits to 640 x 480 graphics input VSVGC (pin F1) LOW 4 : 2 : 2 Y-CB-CR graphics input (format 0)
HIGH 4 : 4 : 4 RGB graphics input (format 3) CBO (pin G3) LOW input demultiplex phase: LSB = LOW
HIGH input demultiplex phase: LSB = HIGH HSVGC (pin E3) LOW input demultiplex phase: MSB = LOW
HIGH input demultiplex phase: MSB = HIGH TTXRQ_XCLKO2 (pin C4) LOW slave (FSVGC, VSVGC and HSVGC are inputs, internal colour bar is active)
A 32 x 32 dots cursor can be overlaid as an option; the bit map of the cursor can be uploaded by an I2C-bus write access to specific registers or in the pixel data input via the PD port. In the latter case the 256 bytes defining the cursor bit map (2 bits per pixel) are expected immediately following the last RGB LUT data in the line preceding the first active line. The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these bits depends on the CMODE I2C-bus register as described in Table 5. Transparent means that the input pixels are passed through, the `cursor colours' can be programmed in separate registers. The bit map is stored with 4 pixels per byte, aligned to the least significant bit. So the first pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The first index is the column, followed by the row; index 0,0 is the upper left corner.
HIGH master (FSVGC, VSVGC and HSVGC are outputs) 8.2 Input formatter
The input formatter converts all accepted PD input data formats, either RGB or Y-CB-CR, to a common internal RGB or Y-CB-CR data stream. When double-edge clocking is used, the data is internally split into portions PPD1 and PPD2. The clock edge assignment must be set according to the I2C-bus control bits SLOT and EDGE for correct operation. 2004 Jun 29 19
Philips Semiconductors
Product specification
HD-CODEC
Table 3 D7 D1 Layout of a byte in the cursor bit map D6 D0 D5 D1 D4 D0 D3 D1 D2 D0 D1 D1 D0 D0 Table 5
SAA7108AE; SAA7109AE
Cursor modes CURSOR MODE CMODE = 0 first cursor colour transparent inverted input CMODE = 1 first cursor colour transparent auxiliary cursor colour
pixel n + 3
pixel n + 2
pixel n + 1
pixel n
CURSOR PATTERN 00 01 10 11
second cursor colour second cursor colour
For each direction, there are 2 registers controlling the position of the cursor, one controls the position of the `hot spot', the other register controls the insertion position. The hot spot is the `tip' of the pointer arrow. It can have any position in the bit map. The actual position registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner. While it is not possible to move the hot spot beyond the left respectively upper screen border this is perfectly legal for the right respectively lower border. It should be noted that the cursor position is described relative to the input resolution. Table 4 BYTE 0 1 2 ... 6 7 ... 254 255 Cursor bit map D7 D6 D5 D4 D3 D2 D1 D0
8.5
RGB Y-CB-CR matrix
RGB input signals to be encoded to PAL or NTSC are converted to the Y-CB-CR colour space in this block. The colour difference signals are fed through low-pass filters and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream for further processing. A gain adjust option corrects the level swing of the graphics world (black-to-white as 0 to 255) to the required range of 16 to 235. The matrix and formatting blocks can be bypassed for Y-CB-CR graphics input. When the auxiliary VGA mode is selected, the output of the cursor insertion block is immediately directed to the triple DAC. 8.6 Horizontal scaler
row 0 column 3 row 0 column 7
row 0 column 2 row 0 column 6
row 0 column 1 row 0 column 5
row 0 column 0 row 0 column 4 row 0 column 8 ...
row 0 row 0 row 0 column 11 column 10 column 9 ... ... ...
row 0 row 0 row 0 row 0 column 27 column 26 column 25 column 24 row 0 row 0 row 0 row 0 column 31 column 30 column 29 column 28 ... ... ... ... row 31 row 31 row 31 row 31 column 27 column 26 column 25 column 24 row 31 row 31 row 31 row 31 column 31 column 30 column 29 column 28
The high quality horizontal scaler operates on the 4 : 2 : 2 data stream. Its control engines compensate the colour phase offset automatically. The scaler starts processing after a programmable horizontal offset and continues with a number of input pixels. Each input pixel is a programmable fraction of the current output pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor to 1. If the SAA7108AE; SAA7109AE input data is in accordance with "ITU-R BT.656", the scaler enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling will occur. The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. Small FIFOs rearrange a 4 : 2 : 2 data stream at the scaler output.
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Philips Semiconductors
Product specification
HD-CODEC
8.7 Vertical scaler and anti-flicker filter 8.10
SAA7108AE; SAA7109AE
Oscillator and Discrete Time Oscillator (DTO)
The functions scaling, Anti-Flicker Filter (AFF) and re-interlacing are implemented in the vertical scaler. Besides the entire input frame, it receives the first and last lines of the border to allow anti-flicker filtering. The circuit generates the interlaced output fields by scaling down the input frames with different offsets for odd and even fields. Increasing the YSKIP setting reduces the anti-flicker function. A YSKIP value of 4095 switches it off; see Table 120. An additional, programmable vertical filter supports the anti-flicker function. This filter is not available at upscaling factors of more than 2. The programming is similar to the horizontal scaler. For the re-interlacing, the resolutions of the offset registers are not sufficient, so the weighting factors for the first lines can also be adjusted. YINC = 0 sets the scaling factor to 1; YIWGTO and YIWGTE must not be 0. Due to the re-interlacing, the circuit can perform upscaling by a maximum factor of 2. The maximum factor depends on the setting of the anti-flicker function and can be derived from the formulae given in Section 8.20. An additional upscaling mode enables the upscaling factor to be increased to a maximum of 4 as it is required for the old VGA modes like 320 x 240. 8.8 FIFO
The master clock generation is realized as a 27 MHz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd-harmonic crystal. The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and the I2C-bus control block. It also usually supplies the triple DAC, with the exception of the auxiliary VGA mode, where the triple DAC is clocked by the pixel clock (PIXCLK). The DTO can be programmed to synthesize all relevant pixel clock frequencies between circa 40 and 85 MHz. Two programmable dividers provide the actual clock to be used externally and internally. The dividers can be programmed to factors of 1, 2, 4 and 8. For the internal pixel clock, a divider ratio of 8 makes no sense and is thus forbidden. The internal clock can be switched completely to the pixel clock input. In this event, the input FIFO is useless and will be bypassed. The entire pixel clock generation can be locked to the vertical frequency. Both pixel clock dividers get re-initialized every field. Optionally, the DTO can be cleared with each V-sync. At proper programming, this will make the pixel clock frequency a precise multiple of the vertical and horizontal frequencies. This is required for some graphic controllers. 8.11 Low-pass Clock Generation Circuit (CGC)
The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock domain. The write clock is PIXCLK and the read clock is XTAL. An underflow or overflow condition can be detected via the I2C-bus read access. In order to avoid underflows and overflows, it is essential that the frequency of the synthesized PIXCLK matches to the input graphics resolution and the desired scaling factor. 8.9 Border generator
This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking filter for all relevant synthesized pixel clock frequencies. 8.12 8.12.1 Encoder VIDEO PATH
The encoder generates luminance and colour subcarrier output signals from the Y, CB and CR baseband signals, which are suitable for use as CVBS or separate Y and C signals. Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer graphics at pixel clock, fed through the FIFO and border generator, or a ITU-R BT.656 style signal. Luminance is modified in gain and in offset (the offset is programmable in a certain range to enable different black level set-ups). A blanking level can be set after insertion of a fixed synchronization pulse tip level, in accordance with standard composite synchronization schemes.
When the graphics picture is to be displayed as interlaced PAL, NTSC, S-video or RGB on a TV screen, it is desired in many cases not to lose picture information due to the inherent overscanning of a TV set. The desired amount of underscan area, which is achieved through appropriate scaling in the vertical and horizontal direction, can be filled in the border generator with an arbitrary true colour tint.
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Philips Semiconductors
Product specification
HD-CODEC
Other manipulations used for the Macrovision anti-taping process, such as additional insertion of AGC super-white pulses (programmable in height), are supported by the SAA7108AE only. To enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer characteristics of the luminance interpolation filter are illustrated in Figs 7 and 8. Appropriate transients at start/end of active video and for synchronization pulses are ensured. Chrominance is modified in gain (programmable separately for CB and CR), and a standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be used for the Y and C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 5 and 6. The amplitude (beginning and ending) of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. After the succeeding quadrature modulator, colour is provided on the subcarrier in 10-bit resolution. The numeric ratio between the Y and C outputs is in accordance with the standards. 8.12.2 TELETEXT INSERTION AND ENCODING (NOT
SIMULTANEOUSLY WITH REAL-TIME CONTROL)
SAA7108AE; SAA7109AE
8.12.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING
Five bytes of VPS information can be loaded via the I2C-bus and will be encoded in the appropriate format into line 16. 8.12.4 CLOSED CAPTION ENCODER
Using this circuit, data in accordance with the specification of Closed Caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number in which data is to be encoded, can be modified in a certain range. The data clock frequency is in accordance with the definition for NTSC M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode Closed Caption data for 50 Hz field frequencies at 32 times the horizontal line frequency. 8.12.5 ANTI-TAPING (SAA7108AE ONLY)
For more information contact your nearest Philips Semiconductors sales office. 8.13 RGB processor
Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock. At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at input pin TTX_SRES. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both fields. The internal insertion window for text is set to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Fig.51. Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz.
This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Before Y, CB and CR signals are de-matrixed, individual gain adjustment for Y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. The transfer curves of luminance and colour difference components of RGB are illustrated in Figs 9 and 10. 8.14 Triple DAC
Both Y and C signals are converted from digital-to-analog in a 10-bit resolution at the output of the video encoder. Y and C signals are also combined into a 10-bit CVBS signal. The CVBS output signal occurs with the same processing delay as the Y, C and optional RGB or CR-Y-CB outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 1516 with respect to Y and C DACs to make maximum use of the conversion ranges.
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Philips Semiconductors
Product specification
HD-CODEC
RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 10-bit resolution. The reference currents of all three DACs can be adjusted individually in order to adapt for different output signals. In addition, all reference currents can be adjusted commonly to compensate for small tolerances of the on-chip band gap reference voltage. Alternatively, all currents can be switched off to reduce power dissipation. All three outputs can be used to sense for an external load (usually 75 ) during a pre-defined output. A flag in the I2C-bus status byte reflects whether a load is applied or not. An automatic sense mode can also be activated, which will immediately indicate any 75 load at any of the three outputs at the dedicated interrupt pin TVD. If the SAA7108AE; SAA7109AE is required to drive a second (auxiliary) VGA monitor or an HDTV set, the DACs receive the signal coming from the HD data path. In this event, the DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video encoder. 8.15 HD data path
SAA7108AE; SAA7109AE
Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data stream via PD7 to PD0. Only vertical frequencies of 50 and 60 Hz are allowed with the SAA7108AE; SAA7109AE. In slave mode, it is not possible to lock the encoders colour carrier to the line frequency with the PHRES bits. In the (more common) master mode, the time base of the circuit is continuously free-running. The IC can output a frame sync at pin FSVGC, a vertical sync at pin VSVGC, a horizontal sync at pin HSVGC and a composite blanking signal at pin CBO. All of these signals are defined in the PIXCLK domain. The duration of HSVGC and VSVGC are fixed, they are 64 clocks for HSVGC and 1 line for VSVGC. The leading slopes are in phase and the polarities can be programmed. The input line length can be programmed. The field length is always derived from the field length of the encoder and the pixel clock frequency that is being used. CBO acts as a data request signal. The circuit accepts input data at a programmable number of clocks after CBO goes active. This signal is programmable and it is possible to adjust the following (see Figs 49 and 50): * The horizontal offset * The length of the active part of the line * The distance from active start to first expected data * The vertical offset separately for odd and even fields * The number of lines per input field. In most cases, the vertical offsets for odd and even fields are equal. If they are not, then the even field will start later. The SAA7108AE; SAA7109AE will also request the first input lines in the even field, the total number of requested lines will increase by the difference of the offsets. As stated above, the circuit can be programmed to accept the look-up and cursor data in the first 2 lines of each field. The timing generator provides normal data request pulses for these lines; the duration is the same as for regular lines. The additional request pulses will be suppressed with LUTL set to logic 0; see Table 143. The other vertical timings do not change in this case, so the first active line can be number 2, counted from 0.
This data path enables the SAA7108AE; SAA7109AE to be used with VGA or HDTV monitors. It receives its data directly from the cursor generator and supports RGB and Y-PB-PR output formats (RGB not with Y-PB-PR input formats). No scaling is done in this mode. A gain adjustment either leads the full level swing to the digital-to-analog converters or reduces the amplitude by a factor of 0.69. This enables sync pulses to be added to the signal as it is required for display units that require signals with sync pulses, either regular or 3-level syncs. 8.16 Timing generator
The synchronization of the SAA7108AE; SAA7109AE is able to operate in two modes; slave mode and master mode. In slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync), VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can be programmed. The frame sync signal is only necessary when the input signal is interlaced, in other cases it may be omitted. If the frame sync signal is present, it is possible to derive the vertical and the horizontal phase from it by setting the HFS and VFS bits. HSVGC and VSVGC are not necessary in this case, so it is possible to switch the pins to output mode.
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Philips Semiconductors
Product specification
HD-CODEC
8.17 Pattern generator for HD sync pulses
SAA7108AE; SAA7109AE
Each index of this table points to a particular line of the next table in the linked list. This table is called the line pattern array and each of the up to seven entries stores up to four pairs of a duration in pixel clock cycles and an index to a value table. The table entries are used to define portions of a line representing a certain value for a certain number of clock cycles. The value specified in this table is actually another 3-bit index into a value array which can hold up to eight 8-bit values. If bit 4 (MSB) of the index is logic 1, the value is inserted into the G or Y signal only; if bit 4 = 0, the associated value is inserted into all three signals. Two additional bits of the entries in the value array (LSBs of the second byte) determine if the associated events appear as a digital pulse on the HSM_CSYNC and/or VSM outputs. To ease the trigger set-up for the sync generation module, a set of registers is provided to set up the screen raster defined as width and height. A trigger position can be specified as an x, y co-ordinate within the overall dimensions of the screen raster. If the x, y counter matches the specified co-ordinates, a trigger pulse is generated which pre-loads the tables with their initial values. Table 6 outlines an example on how to set up the sync tables for a 1080i HD raster. Important note: Due to a problem in the programming interface, writing to the line pattern array (address D2) might destroy the data of the line type array (address D1). A work around is to write the line pattern array data before writing the line type array. Reading of the arrays is possible but all address pointers must be initialized before the next write operation.
The pattern generator provides an appropriate synchronization pattern for the video data path in auxiliary monitor or HDTV mode, respectively. It provides maximum flexibility in terms of raster generation for all interlaced and non-interlaced computer graphics or ATSC formats. The sync engine is capable of providing a combination of event-value pairs which can be used to insert certain values at specified times in the outgoing data stream. It can also be used to generate digital signals associated with time events. They can be used as digital horizontal and vertical synchronization signals on pins HSM_CSYNC and VSM. The picture position is adjustable through the programmable relationship between the sync pulses and the video contents. The generation of embedded analog sync pulses is bound to a number of events which can be defined for a line. Several of these line timing definitions can exist in parallel. For the final sync raster composition a certain sequence of lines with different sync event properties has to be defined. The sequence specifies a series of line types and the number of occurrences of this specific line type. After the sequence has been completed, it restarts from the beginning. All pulse shapes are filtered internally in order to avoid ringing after analog post filters. The sequence of the generated pulse stream must fit precisely to the incoming data stream in terms of the total number of pixels per line and lines per frame. The sync engines flexibility is achieved by using a sequence of linked lists carrying the properties for the image, the lines as well as fractions of lines. Figure 11 illustrates the context between the various tables. The first table serves as an array to hold the correct sequence of lines composing the synchronization raster. It can contain up to 16 entries. Each entry holds a 4-bit index to the next table and a 10-bit counter value which specifies how often this particular line is invoked. If the necessary line count for a particular line exceeds the 10 bits, it has to use two table entries. The 4-bit index in the line count array points to the line type array. It holds up to 15 entries where, index 0 is not used, index 1 points to the first entry, index 2 to the second entry of the line type array etc. Each entry of the line type array can hold up to 8 index pointers to another table. These indices point to portions of a line pulse pattern: A line could be split up e.g. into a sync, a blank, and an active portion followed by another blank portion, occupying four entries in one table line. 2004 Jun 29 24
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth
4-bit line type index
10-bit line count LINE COUNT ARRAY 16 entries line count pointer
3 line type pointer
3
3
3
3
3
3
3 pattern pointer
LINE TYPE ARRAY 15 entries 3 3 3 3 3 3 3 3
event type pointer
10-bit duration
10-bit duration
10-bit duration
10-bit duration
4-bit value index 4-bit value index 4-bit value index 4-bit value index 8 + 2-bit value VALUE ARRAY 8 entries line pattern pointer
MBL797
LINE PATTERN ARRAY 7 entries
Fig.11 Context between the pattern generator tables for DH sync pulses.
2004 Jun 29
25
Philips Semiconductors
Product specification
HD-CODEC
Table 6 Example for set-up of the sync tables
SAA7108AE; SAA7109AE
SEQUENCE Write to subaddress D0H 00 05 20 01 40 0E 60 1C 12 02 60 01 50 04 20 01 30 0F 60 1C 12 02 60
COMMENT
points to first entry of line count array (index 0) generate 5 lines of line type index 2 (remember, it is the second entry of the line type array); will be the first vertical raster pulse generate 1 line of line type index 4; will be sync-black-sync-black sequence after the first vertical pulse generate 14 lines of line type index 6; will be the following lines with sync-black sequence generate 540 lines of line type index 1; will be lines with sync and active video generate 2 lines of line type index 6; will be the following lines with sync-black sequence generate 1 line of line type index 5; will be the following line (line 563) with sync-black-sync-black-null sequence (null is equivalent to sync tip) generate 4 lines of line type index 2; will be the second vertical raster pulse generate 1 line of line type index 3; will be the following line with sync-null-sync-black sequence generate 15 lines of line type index 6; will be the following lines with sync-black sequence generate 540 lines of line type index 1; will be lines with sync and active video generate 2 lines of line type index 6; will be the following lines with sync-black sequence; now, 1125 lines are defined
Write to subaddress D2H (insertion is done into all three analog output signals) 00 6F 33 2B 30 00 00 00 00 6F 43 2B 30 00 00 00 00 2B 10 2B 20 57 30 00 00 Write to subaddress D1H 00 34 00 00 00 24 24 00 00 24 14 00 00 14 14 00 00 14 24 00 00 54 00 00 00 points to first entry of line type array (index 1) use pattern entries 4 and 3 in this sequence (for sync and active video) use pattern entries 4, 2, 4 and 2 in this sequence (for 2 x sync-black-null-black) use pattern entries 4, 2, 4 and 1 in this sequence (for sync-black-null-black-null) use pattern entries 4, 1, 4 and 1 in this sequence (for sync-black-sync-black) use pattern entries 4, 1, 4 and 2 in this sequence (for sync-black-sync-black-null) use pattern entries 4 and 5 in this sequence (for sync-black) points to first entry of line pattern array (index 1) 880 x value(3) + 44 x value(3); (subtract 1 from real duration) 880 x value(4) + 44 x value(3) 44 x value(1) + 44 x value(2) + 88 x value(3)
3B 30 BF 03 BF 03 2B 30 60 x value(3) + 960 x value(0) + 960 x value(0) + 44 x value(3) 3B 30 BF 33 BF 33 2B 30 60 x value(3) + 960 x value(3) + 960 x value(3) + 44 x value(3)
2004 Jun 29
26
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SEQUENCE
COMMENT
Write to subaddress D3H (no signals are directed to pins HSM_CSYNC and VSM) 00 CC 00 80 00 0A 00 CC 00 80 00 Write to subaddress DCH 0B 8.18 I2C-bus interface insertion is active, gain for signal is adapted accordingly So in most cases, DOWNA and DOWND should be set to logic 1 simultaneously. If the EIDIV bit is logic 1, it should be set to logic 0 before power-down. 8.20 Programming the graphics acquisition scaler of the video encoder points to first entry of value array (index 0) black level, to be added during active video sync level LOW (minimum output voltage) sync level HIGH (3-level sync) black level (needed elsewhere) null (identical with sync level LOW)
The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are read and write, except two read only status bytes. The register bit map consists of an RGB Look-Up Table (LUT), a cursor bit map and control registers. The LUT contains three banks of 256 bytes, where each RGB triplet is assigned to one address. Thus a write access needs the LUT address and three data bytes following subaddress FFH. For further write access auto-incrementing of the LUT address is performed. The cursor bit map access is similar to the LUT access but contains only a single byte per address. The I2C-bus slave address is defined as 88H. 8.19 Power-down modes
The encoder section needs to provide a continuous data stream at its analog outputs as well as receive a continuous stream from its data source. Due to the fact that there is no frame memory isolating the data streams, restrictions apply to the input frame timings. Input and output processing of the encoder section are only coupled through the vertical frequencies. In master mode, the encoder provides a vertical sync and an odd/even pulse to the input processing, in slave mode, the encoder receives them. The parameters of the input field are mainly given by the memory capacity of the encoder section. The rule is that the scaler and thus the input processing needs to provide the video data in the same time frames as the encoder reads them. So the vertical active video times (and the vertical frequencies) need to be the same. The second rule is that there has to be data in the buffer FIFO when the encoder enters the active video area. So the vertical offset in the input path needs to be a bit shorter than the offset of the encoder. The following gives the set of equations required to program the IC for the most common application: A post processor in master mode with non-interlaced video input data.
In order to reduce the power consumption, the SAA7108AE; SAA7109AE supports 2 Power-down modes, accessible via the I2C-bus. The analog Power-down mode (DOWNA = 1) turns off the digital-to-analog converters and the pixel clock synthesizer. The digital down mode turns off all internal clocks and sets the digital outputs to LOW except the I2C-bus interface. The IC retains its programming and can still be accessed in this mode, but not all registers can be read from or written to. Reading or writing to the look-up tables, the cursor and the HD sync generator require a valid pixel clock. The typical supply current in full power-down is approximately 5 mA. Due to the fact that the analog Power-down mode turns off the pixel clock synthesizer, there are limitations in some applications. If there is no pixel clock, the IC is not able to set its outputs to LOW. 2004 Jun 29 27
Philips Semiconductors
Product specification
HD-CODEC
Some variables are defined below: * InPix: the number of active pixels per input line * InPpl: the length of the entire input line in pixel clocks * InLin: the number of active lines per input field/frame * TPclk: the pixel clock period * RiePclk: the ratio of internal to external pixel clock * OutPix: the number of active pixels per output line * OutLin: the number of active lines per output field * TXclk: the encoder clock period (37.037 ns). 8.20.1 TV DISPLAY WINDOW
SAA7108AE; SAA7109AE
262.5 x 1716 x TXclk Thus: TPclk = --------------------------------------------------------------------------------------- (60 Hz) InLin + 2 --------------------- x 262.5 InPpl x integer OutLin 312.5 x 1728 x TXclk TPclk = --------------------------------------------------------------------------------------- (50 Hz) InLin + 2 InPpl x integer --------------------- x 312.5 OutLin and for the pixel clock generator TXclk 20 + PCLE PCL = -------------- x 2 (all frequencies); TPclk see Tables 102, 104 and 105. The divider PCLE should be set according to Table 104. PCLI may be set to a lower or the same value. Setting a lower value means that the internal pixel clock is higher and the data get sampled up. The difference may be 1 at 640 x 480 pixels resolution and 2 at resolutions with 320 pixels per line as a rule of thumb. This allows horizontal upscaling by a maximum factor of 2 respectively 4 (this is the parameter RiePclk). log RiePclk PCLI = PCLE - ---------------------------- (all frequencies) log 2 The equations ensure that the last line of the field has the full number of clock cycles. Many graphic controllers require this. Note that the bit PCLSY needs to be set to ensure that there is not even a fraction of a clock left at the end of the field. 8.20.3 HORIZONTAL SCALER
At 60 Hz, the first visible pixel has the index 256, 710 pixels can be encoded; at 50 Hz, the index is 284, 702 pixels can be visible. The output lines should be centred on the screen. It should be noted that the encoder has 2 clocks per pixel; see Table 93. ADWHS = 256 + 710 - OutPix (60 Hz); ADWHS = 284 + 702 - OutPix (50 Hz); ADWHE = ADWHS + OutPix x 2 (all frequencies) For vertical, the procedure is the same. At 60 Hz, the first line with video information is number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see Table 99. 240 - OutLin FAL = 19 + -------------------------------- (60 Hz); 2 287 - OutLin FAL = 23 + -------------------------------- (50 Hz); 2 LAL = FAL + OutLin (all frequencies) Most TV sets use overscan, and not all pixels respectively lines are visible. There is no standard for the factor, it is highly recommended to make the number of output pixels and lines adjustable. A reasonable underscan factor is 10 %, giving approximately 640 output pixels per line. 8.20.2 INPUT FRAME AND PIXEL CLOCK
XOFS can be chosen arbitrarily, the condition being that XOFS + XPIX HLEN is fulfilled. Values given by the VESA display timings are preferred. HLEN = InPpl x RiePclk - 1 InPix XPIX = ------------ x RiePclk 2 4096 OutPix XINC = ----------------- x ------------------InPix RiePclk XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1. 8.20.4 VERTICAL SCALER
The total number of pixel clocks per line and the input horizontal offset need to be chosen next. The only constraint is that the horizontal blanking has at least 10 clock pulses. The required pixel clock frequency can be determined in the following way: Due to the limited internal FIFO size, the input path has to provide all pixels in the same time frame as the encoders vertical active time. The scaler also has to process the first and last border lines for the anti-flicker function. 2004 Jun 29 28
The input vertical offset can be taken from the assumption that the scaler should have just finished writing the first line when the encoder starts reading it: FAL x 1716 x TXclk YOFS = --------------------------------------------------- - 2.5 (60 Hz) InPpl x TPclk FAL x 1728 x TXclk YOFS = --------------------------------------------------- - 2.5 (50 Hz) InPpl x TPclk
Philips Semiconductors
Product specification
HD-CODEC
In most cases the vertical offsets will be the same for odd and even fields. The results should be rounded down. YPIX = InLin YSKIP defines the anti-flicker function. 0 means maximum flicker reduction but minimum vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth. Note that the maximum value for YINC is 4095. It might be necessary to reduce the value of YSKIP to fulfil this requirement. OutLin YSKIP YINC = --------------------- x 1 + ---------------- x 4096 InLin + 2 4095 YINC YIWGTO = ------------- + 2048 2 YINC - YSKIP YIWGTE = ------------------------------------2 When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE positive. Note that these equations assume that the input is non-interlaced while the output is interlaced. If the input is interlaced, the initial weighting factors need to be adapted to get the proper phase offsets in the output frame. If vertical upscaling beyond the upper capabilities is required, the parameter YUPSC may be set to 1. This extends the maximum vertical scaling factor by a factor 2. Only the parameter YINC gets affected, it needs to be divided by 2 to get the same effect. There are restrictions in this mode: * The vertical filter YFILT is not available in this mode; the circuit will ignore this value * The horizontal blanking needs to be long enough to transfer an output line between 2 memory locations. This is 710 internal pixel clocks Or the upscaling factor needs to be limited to 1.5 and the horizontal upscaling factor is also limited to less than 1.5. In this case a normal blanking length is sufficient. 8.21 Input levels and formats
SAA7108AE; SAA7109AE
For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated for by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. The RGB, respectively CR-Y-CB path features an individual gain setting for luminance (GY) and colour difference signals (GCD). Reference levels are measured with a colour bar, 100 % white, 100 % amplitude and 100 % saturation. The encoder section of the SAA7108AE; SAA7109AE has special input cells for the VGC port. They operate at a wider supply voltage range and have a strict input threshold at 1/2VDD(DVO). To achieve full speed of these cells, the EIDIV bit needs to be set to logic 1. In this case the impedance of these cells is approximately 6 k. This may cause trouble with the bootstrapping pins of some graphic chips. So the power-on reset forces the bit to logic 0, the input impedance is regular in this mode. Table 7
"ITU-R BT.601" signal component levels
SIGNALS(1)
COLOUR Y White Yellow Cyan Green Magenta Red Blue Black Note 1. Transformation: a) R = Y + 1.3707 x (CR - 128) b) G = Y - 0.3365 x (CB - 128) - 0.6982 x (CR - 128) c) B = Y + 1.7324 x (CB - 128). 235 210 170 145 106 81 41 16 CB 128 16 166 54 202 90 240 128 CR 128 146 16 34 222 240 110 128 R 235 235 16 16 235 235 16 16 G 235 235 235 235 16 16 16 16 B 235 16 235 16 235 16 235 16
The SAA7108AE; SAA7109AE accepts digital Y, CB, CR or RGB data with levels (digital codes) in accordance with "ITU-R BT.601". An optional gain adjustment also allows data to be accepted with the full level swing of 0 to 255.
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Philips Semiconductors
Product specification
HD-CODEC
Table 8 Usage of bits SLOT and EDGE DATA SLOT CONTROL (EXAMPLE FOR FORMAT 0) SLOT EDGE 0 0 1 1 0 1 0 1 1st DATA at rising edge G3/Y3 at falling edge G3/Y3 at rising edge R7/CR7 at falling edge R7/CR7 2nd DATA at falling edge R7/CR7 at rising edge R7/CR7 at falling edge G3/Y3 at rising edge G3/Y3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Table 9 Pin assignment for input format 0 8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED RGB/CB-Y-CR PIN PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 FALLING CLOCK EDGE G3/Y3 G2/Y2 G1/Y1 G0/Y0 B7/CB7 B6/CB6 B5/CB5 B4/CB4 B3/CB3 B2/CB2 B1/CB1 B0/CB0 RISING CLOCK EDGE R7/CR7 R6/CR6 R5/CR5 R4/CR4 R3/CR3 R2/CR2 R1/CR1 R0/CR0 G7/Y7 G6/Y6 G5/Y5 G4/Y4 PIN PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
SAA7108AE; SAA7109AE
Table 10 Pin assignment for input format 1 5 + 5 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB PIN FALLING CLOCK EDGE G2 G1 G0 B4 B3 B2 B1 B0 RISING CLOCK EDGE X R4 R3 R2 R1 R0 G4 G3
Table 11 Pin assignment for input format 2 5 + 6 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB PIN FALLING CLOCK EDGE G2 G1 G0 B4 B3 B2 B1 B0 RISING CLOCK EDGE R4 R3 R2 R1 R0 G5 G4 G3
Table 12 Pin assignment for input format 3 8 + 8 + 8-BIT 4 : 2 : 2 NON-INTERLACED CB-Y-CR FALLING CLOCK EDGE n CB7(0) CB6(0) CB5(0) CB4(0) CB3(0) CB2(0) CB1(0) CB0(0) RISING CLOCK EDGE n Y7(0) Y6(0) Y5(0) Y4(0) Y3(0) Y2(0) Y1(0) Y0(0) FALLING CLOCK EDGE n+1 CR7(0) CR6(0) CR5(0) CR4(0) CR3(0) CR2(0) CR1(0) CR0(0) RISING CLOCK EDGE n+1 Y7(1) Y6(1) Y5(1) Y4(1) Y3(1) Y2(1) Y1(1) Y0(1)
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
2004 Jun 29
30
Philips Semiconductors
Product specification
HD-CODEC
Table 13 Pin assignment for input format 4 8 + 8 + 8-BIT 4 : 2 : 2 INTERLACED CB-Y-CR (ITU-R BT.656, 27 MHz CLOCK) RISING CLOCK EDGE n CB7(0) CB6(0) CB5(0) CB4(0) CB3(0) CB2(0) CB1(0) CB0(0) RISING CLOCK EDGE n+1 Y7(0) Y6(0) Y5(0) Y4(0) Y3(0) Y2(0) Y1(0) Y0(0) RISING CLOCK EDGE n+2 CR7(0) CR6(0) CR5(0) CR4(0) CR3(0) CR2(0) CR1(0) CR0(0) RISING CLOCK EDGE n+3 Y7(1) Y6(1) Y5(1) Y4(1) Y3(1) Y2(1) Y1(1) Y0(1)
SAA7108AE; SAA7109AE
Table 15 Pin assignment for input format 6 8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED RGB/CB-Y-CR PIN PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 FALLING CLOCK EDGE G4/Y4 G3/Y3 G2/Y2 B7/CB7 B6/CB6 B5/CB5 B4/CB4 B3/CB3 G0/Y0 B2/CB2 B1/CB1 B0/CB0 RISING CLOCK EDGE R7/CR7 R6/CR6 R5/CR5 R4/CR4 R3/CR3 G7/Y7 G6/Y6 G5/Y5 R2/CR2 R1/CR1 R0/CR0 G1/Y1
PIN
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Table 14 Pin assignment for input format 5; note 1 8-BIT NON-INTERLACED INDEX COLOUR PIN PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Note 1. X = don't care. FALLING CLOCK EDGE X X X X INDEX7 INDEX6 INDEX5 INDEX4 INDEX3 INDEX2 INDEX1 INDEX0 RISING CLOCK EDGE X X X X X X X X X X X X
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31
Philips Semiconductors
Product specification
HD-CODEC
9 9.1 9.1.1 FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO DECODER PART Decoder ANALOG INPUT PROCESSING
SAA7108AE; SAA7109AE
The SAA7108AE; SAA7109AE offers six analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see Fig.15. 9.1.2 ANALOG CONTROL CIRCUITS
The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. The characteristics are illustrated in Fig.12. During the vertical blanking period, gain and clamping control is frozen.
MGD138
6 V (dB) 0 -6 -12 -18 -24 -30 -36 -42
0
2
4
6
8
10
12
f (MHz)
14
Fig.12 Anti-alias filter.
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32
Philips Semiconductors
Product specification
HD-CODEC
9.1.2.1 Clamping
SAA7108AE; SAA7109AE
The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, which is matched to the ADCs input voltage range. The AGC active time is the sync bottom of the video signal. Signal (white) peak control limits the gain at signal overshoots. The influence of supply voltage variation within the specified range is automatically eliminated by clamping and automatic gain control. The flow charts show more details of the AGC; see Figs 16 and 17.
The clamping control circuit controls the correct clamping of the analog input signals. A coupling capacitor is used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (60) and chrominance (128). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal.
9.1.2.2
Gain control
The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers, or controls one of these amplifiers automatically via a built-in Automatic Gain Control (AGC) as part of the Analog Input Control (AICO).
TV line analog line blanking 255 analog input level +3 dB 0 dB 60 1 HCL HSY
MGL065
controlled ADC input level
maximum
GAIN
CLAMP
range 9 dB
(1 V (p-p) 18/56 ) -6 dB minimum
MHB325
0 dB
Fig.13 Analog line with clamp (HCL) and gain range (HSY).
Fig.14 Automatic gain range.
2004 Jun 29
33
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ndbook, full pagewidth
2004 Jun 29
AI24 AI23 AI2D AI22 AI21 P6 P7 P8 P9 P10 SOURCE SWITCH ANALOG AMPLIFIER DAC9 CLAMP CIRCUIT AI12 AI1D AI11 P11 P12 P13 SOURCE SWITCH CLAMP CIRCUIT ANALOG AMPLIFIER DAC9
Philips Semiconductors
HD-CODEC
TEST SELECTOR AND BUFFER AOSL [1:0]
M10
AOUT
ANTI-ALIAS FILTER
BYPASS SWITCH
ADC2
FUSE [1:0]
ANTI-ALIAS FILTER
BYPASS SWITCH
ADC1
FUSE [1:0]
34
MODE CONTROL CLAMP CONTROL GAIN CONTROL ANTI-ALIAS CONTROL VERTICAL BLANKING CONTROL MODE3 MODE2 MODE1 MODE0 HCL GLIMB HSY GLIMT WIPA SLTCA HOLDG GAFIX WPOFF GUDL [1:0] GAI [28:20] GAI [18:10] HLNRS UPTCV VBSL VBLNK SVREF 9 9
SAA7108AE; SAA7109AE
ANALOG CONTROL
CROSS MULTIPLEXER 9 CVBS/LUM 9 CVBS/CHR 9 9
MHB892
Product specification
AD2BYP AD1BYP
Fig.15 Analog input processing using the SAA7108AE; SAA7109AE as differential front-end with 9-bit ADC.
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
ANALOG INPUT AMPLIFIER ANTI-ALIAS FILTER ADC 9 LUMA/CHROMA DECODER gain DAC 9
NO ACTION
1
VBLK 1
0 0 0 1 0
HOLDG 1
X
HSY
0 0 1
> 254
1 1 0 1 0
<4
<1
> 254
X=0 1 > 248 0
X=1
+1/F STOP
+1/L
-1/LLC2
+1/LLC2
-1/LLC2
+/- 0
GAIN ACCUMULATOR (18 BITS) ACTUAL GAIN VALUE 9-BIT (AGV) [-3/+6 dB] 1 0 1
X
HSY 1
0 0
Y
AGV X = system variable. Y = (IAGV - FGVI) > GUDL. VBLK = vertical blanking pulse. HSY = horizontal sync pulse. AGV = actual gain value. FGV = frozen gain value.
UPDATE
FGV
GAIN VALUE 9-BIT
MHB531
Fig.16 Gain flow chart.
2004 Jun 29
35
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
ANALOG INPUT ADC
NO BLANKING ACTIVE
1
VBLK
0
<- CLAMP
GAIN ->
1
HCL
0
1
HSY
0
1
CLL
0
0
SBOT
1
1
WIPE
0
+ CLAMP
- CLAMP
NO CLAMP
+ GAIN
- GAIN
fast - GAIN
slow + GAIN
MGC647
WIPE = white peak level (254). SBOT = sync bottom level (1). CLL = clamp level [60 Y (128 C)]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse.
Fig.17 Clamp and gain flow.
2004 Jun 29
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CVBS-IN or Y-IN LDEL YCOMB DELAY COMPENSATION CHR QUADRATURE MODULATOR UV INTERPOLATION LOW-PASS 3 LUFI [ 3:0] CSTD [ 2:0] YDEL [ 2:0] SET_RAW SET_VBI Y SUBTRACTOR LUMINANCE-PEAKING OR LOW-PASS, Y-DELAY ADJUSTMENT Y/CVBS DBRI [ 7:0] DCON [ 7:0] DSAT [ 7:0] RAWG [ 7:0] RAWO [ 7:0] COLO LUBW UV CVBS-IN or CHR-IN QUADRATURE DEMODULATOR LOW-PASS 1 DOWNSAMPLING ADAPTIVE COMB FILTER UV LOW-PASS 2 BRIGHTNESS CONTRAST SATURATION CONTROL RAW DATA GAIN AND OFFSET CONTROL Y-OUT/ CVBS-OUT UV-OUT SUBCARRIER GENERATION 2 LCBW [ 2:0] SET_RAW CCOMB SET_VBI YCOMB LDEL BYPS CHBW HREF-OUT CHROMINANCE INCREMENT DELAY LDEL YCOMB SECAM PROCESSING
9.1.3 CHROMINANCE AND LUMINANCE PROCESSING
Philips Semiconductors
HD-CODEC
Fig.18 Chrominance and luminance processing.
handbook, full pagewidth
37
SUBCARRIER GENERATION 1 HUEC
UV CHROMINANCE INCREMENT DTO-RESET SUBCARRIER INCREMENT GENERATION AND DIVIDER PHASE DEMODULATOR AMPLITUDE DETECTOR BURST GATE ACCUMULATOR LOOP FILTER
SET_RAW SET_VBI
CHROMA GAIN CONTROL PAL DELAY LINE UVADJUSTMENT SECAM RECOMBINATION
SAA7108AE; SAA7109AE
CDTO INCS CSTD [ 2:0] RTCO
FCTC ACGC CGAIN [ 6:0] IDEL [ 3:0]
CODE
SECS
SET_RAW SET_VBI
DCVF
MHB532
Product specification
fH /2 switch signal
Philips Semiconductors
Product specification
HD-CODEC
9.1.3.1 Chrominance path
SAA7108AE; SAA7109AE
* Baseband `bell' filters to reconstruct the amplitude and phase equalized 0 and 90 FM signals * Phase demodulator and differentiator (FM demodulation) * De-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal). The succeeding chrominance gain control block amplifies or attenuates the CB-CR signal according to the required ITU 601/656 levels. It is controlled by the output signal from the amplitude detection circuit within the burst processing block. The burst processing block provides the feedback loop of the chrominance PLL and contains the following: * Burst gate accumulator * Colour identification and killer * Comparison nominal/actual burst amplitude (PAL/NTSC standards only) * Loop filter chrominance gain control (PAL/NTSC standards only) * Loop filter chrominance PLL (only active for PAL/NTSC standards) * PAL/SECAM sequence detection, H/2-switch generation. The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals). The PAL delay line block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards, the delay line can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1. It is always disabled during VBI or raw data lines programmable by the LCRn registers (subaddresses 41H to 57H); see Section 9.2. The embedded line delay is also used for SECAM recombination (cross-over switches).
The 9-bit CVBS or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0 and 90 phase relationship to the demodulator axis). The frequency is dependent on the chosen colour standard. The time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1). Eight characteristics are programmable via LCBW3 to LCBW0 to achieve the desired bandwidth for the colour difference signals (PAL, NTSC) or the 0 and 90 FM signals (SECAM). The chrominance low-pass 1 characteristic also influences the grade of cross-luminance reduction during horizontal colour transients (large chrominance bandwidth means strong suppression of cross-luminance). If the Y comb filter is disabled when YCOMB = 0 the filter directly influences the width of the chrominance notch within the luminance path (large chrominance bandwidth means wide chrominance notch resulting to lower luminance bandwidth). The low-pass filtered signals are fed to the adaptive comb filter block. The chrominance components are separated from the luminance via a two-line vertical stage (four lines for PAL standards) and a decision logic circuit between the filtered and the non-filtered output signals: this block is bypassed for SECAM signals. The comb filter logic can be enabled independently for the succeeding luminance and chrominance processing by YCOMB (subaddress 09H, bit 6) and/or CCOMB (subaddress 0EH, bit 0). It is always bypassed during VBI or raw data lines, programmable by the LCRn registers (subaddresses 41H to 57H); see Section 9.2. The separated CB-CR components are further processed by a second filter stage (low-pass 2) to modify the chrominance bandwidth without influencing the luminance path. It's characteristic is controlled by CHBW (subaddress 10H, bit 3). For the complete transfer characteristic of low-pass filters 1 and 2 see Figs 19 and 20. The SECAM processing (bypassed for QAM standards) contains the following blocks:
2004 Jun 29
38
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -48 -51 -54 -57 -60 0
(1) (2) (3) (4)
MHB533
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz)
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz)
(5) (6) (7) (8)
Fig.19 Transfer characteristics of the chrominance low-pass at CHBW = 0.
2004 Jun 29
39
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -48 -51 -54 -57 -60 0
(1) (2) (3) (4)
MHB534
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz)
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -48 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz)
(5) (6) (7) (8)
Fig.20 Transfer characteristics of the chrominance low-pass at CHBW = 1.
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40
Philips Semiconductors
Product specification
HD-CODEC
9.1.3.2 Luminance path
SAA7108AE; SAA7109AE
The frequency characteristic of the separated luminance signal can be further modified by the succeeding luminance filter block. It can be configured as peaking (resolution enhancement) or low-pass block by LUFI3 to LUFI0 (subaddress 09H, bits 3 to 0). The 16 resulting frequency characteristics can be seen in Fig.25. The LUFI3 to LUFI0 settings can be used as a user programmable sharpness control. The luminance filter block also contains the adjustable Y delay part; programmable by YDEL2 to YDEL0 (subaddress 11H, bits 2 to 0).
The rejection of the chrominance components within the 9-bit CVBS or Y input signal is done by subtracting the re-modulated chrominance signal from the CVBS input. The comb filtered CB-CR components are interpolated (upsampled) by the low-pass 3 block. It's characteristic is controlled by LUBW (subaddress 09H, bit 4) to modify the width of the chrominance `notch' without influencing the chrominance path. The programmable frequency characteristics available, in conjunction with the LCBW2 to LCBW0 settings, can be seen in Figs 21 to 24. It should be noted that these frequency curves are only valid for Y comb disabled filter mode (YCOMB = 0). In comb filter mode the frequency response is flat. The centre frequency of the notch is automatically adapted to the chosen colour standard. The interpolated CB-CR samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. This second DTO is locked to the first subcarrier generator by an increment delay circuit matched to the processing delay, which is different for PAL and NTSC standards according to the chosen comb filter algorithm. The two modulated signals are finally added to create the re-modulated chrominance signal.
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41
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -51 -54 -57 -60
(1) (2) (3) (4)
MHB535
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
(5) (6) (7) (8)
Fig.21 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at LUBW = 0.
2004 Jun 29
42
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) LCBW[2:0] = 000 LCBW[2:0] = 010 LCBW[2:0] = 100 LCBW[2:0] = 110 -51 -54 -57 -60
(1) (2) (3) (4)
MHB536
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (5) (6) (7) (8) LCBW[2:0] = 001 LCBW[2:0] = 011 LCBW[2:0] = 101 LCBW[2:0] = 111 -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
(5) (6) (7) (8)
Fig.22 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at LUBW =1.
2004 Jun 29
43
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -51 -54 -57 -60
(1) (2) (3) (4)
MHB537
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
(5) (6) (7) (8)
Fig.23 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at LUBW = 0.
2004 Jun 29
44
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. -51 -54 -57 -60
(1) (2) (3) (4)
MHB538
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. -51 -54 -57 -60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz)
(5) (6) (7) (8)
Fig.24 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at LUBW = 1.
2004 Jun 29
45
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
MHB539
9 V (dB) 8
(1) (2)
7 6 5 4 3 (1) (2) (3) (4) (5) (6) (7) (8) LUFI[3:0] = 0001. LUFI[3:0] = 0010. LUFI[3:0] = 0011. LUFI[3:0] = 0100. LUFI[3:0] = 0101. LUFI[3:0] = 0110. LUFI[3:0] = 0111. LUFI[3:0] = 0000. 2 1 0 -1 0 3 V (dB) 0 -3 -6 -9 -12 -15 -18 -21 (9) LUFI[3:0] = 1000. (10) LUFI[3:0] = 1001. (11) LUFI[3:0] = 1010. (12) LUFI[3:0] = 1011. (13) LUFI[3:0] = 1100. (14) LUFI[3:0] = 1101. (15) LUFI[3:0] = 1110. (16) LUFI[3:0] = 1111. -24 -27 -30 -33 -36 -39 0 0.5 1.0 0.5 1.0
(3) (4) (5) (6) (7) (8)
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0 5.5 f (MHz)
6.0
(9) (10) (11) (12) (13) (14) (15) (16)
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0 5.5 f (MHz)
6.0
Fig.25 Transfer characteristics of the luminance peaking/low-pass filter (sharpness).
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46
Philips Semiconductors
Product specification
HD-CODEC
9.1.3.3
SAA7108AE; SAA7109AE
Brightness Contrast Saturation (BCS) control and decoder output levels
The resulting Y (CVBS) and CB-CR signals are fed to the BCS block, which contains the following functions: * Chrominance saturation control by DSAT7 to DSAT0 * Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0 * Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0 * Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil "ITU Recommendation 601/656".
+255 handbook, full pagewidth +235 white
+255 +240 +212
blue 100% blue 75%
+255 +240 +212
red 100% red 75%
+128
LUMINANCE 100%
+128
colourless CB-COMPONENT
+128
colourless CR-COMPONENT
+44 +16 0 black +16 0
yellow 75% yellow 100%
+44 +16 0
cyan 75% cyan 100%
MHB730
a. Y output range.
b. CB output range.
c. CR output range.
"ITU Recommendation 601/656" digital levels with default BCS (decoder) settings DCON[7:0] = 44H, DBRI[7:0] = 80H and DSAT[7:0] = 40H. Equations for modification to the Y-CB-CR levels via BCS control I2C-bus bytes DBRI, DCON and DSAT.
Luminance: DCON Y OUT = Int ---------------- x ( Y - 128 ) + DBRI 68
DSAT Chrominance: ( C R C B ) OUT = Int --------------- x ( C R, C B - 128 ) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with "ITU Recommendation 601/656".
Fig.26 Y-CB-CR range for scaler input and X port output.
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47
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
+255 +209 white
+255 +199 white
LUMINANCE
LUMINANCE
+71 +60 SYNC 1
black black shoulder
+60 SYNC
black shoulder = black
sync bottom
1
sync bottom
MGD700
a. Sources containing 7.5 IRE black level offset (e.g. NTSC M).
b. Sources not containing black level offset.
CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128. Equation for modification of the raw data levels via bytes RAWG and RAWO: RAWG CVBS OUT = Int ----------------- x ( CVBS nom - 128 ) + RAWO 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with "ITU Recommendation 601/656".
Fig.27 CVBS (raw data) range for scaler input, data slicer and X port output.
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48
Philips Semiconductors
Product specification
HD-CODEC
9.1.4 SYNCHRONIZATION
SAA7108AE; SAA7109AE
The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is a multiple of the line frequency: 6.75 MHz = 429 x fH (50 Hz), or 6.75 MHz = 432 x fH (60 Hz). The LFCO signal is multiplied internally by a factor of 2 and 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50 % duty cycle. Table 16 Decoder clock frequencies CLOCK XTAL LLC LLC2 LLC4 (internal) LLC8 (virtual) FREQUENCY (MHz) 24.576 or 32.110 27 13.5 6.75 3.375
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz by a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the line frequency control signal (LFCO); see Fig.28. The detection of `pseudo syncs' as part of the Macrovision copy protection standard is also done within the synchronization circuit. The result is reported as flag COPRO within the decoder status byte at subaddress 1FH. 9.1.5 CLOCK GENERATION CIRCUIT
The internal CGC generates all clock signals required for the video input processor.
LFCO
BAND PASS FC = LLC/4
ZERO CROSS DETECTION
PHASE DETECTION
LOOP FILTER
OSCILLATOR
LLC
DIVIDER 1/2
DIVIDER 1/2
MHB330
LLC2
Fig.28 Block diagram of the clock generation circuit.
9.1.6
POWER-ON RESET AND CE INPUT
A missing clock, insufficient digital or analog VDDAd supply voltages (below 2.7 V) will start the reset sequence; all outputs are forced to 3-state (see Fig.29). The indicator output RESd is LOW for approximately 128 LLC after the internal reset and can be applied to reset other circuits of the digital TV system. It is possible to force a reset by pulling the Chip Enable (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2 and SDAd return from 3-state to active, while the other signals have to be activated via programming.
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
POC V
DDA ANALOG
POC V
DDD DIGITAL
CLOCK PLL LLC CE POC LOGIC RESINT CLK0 POC DELAY RES
CE
XTALO
LLCINT
RESINT
LLC
RES (internal reset)
some ms
20 to 200 s PLL-delay <1 ms
896 LCC digital delay
128 LCC
MHB331
POC = Power-on Control. CE = chip enable input. XTALO = crystal oscillator output. LLCINT = internal system clock. RESINT = internal reset. LLC = line-locked clock output. RES = reset output.
Fig.29 Power-on control circuit.
2004 Jun 29
50
Philips Semiconductors
Product specification
HD-CODEC
9.2 Decoder output formatter
SAA7108AE; SAA7109AE
For each LCR value, from 2 to 23, the data type can be programmed individually. LCR2 to LCR23 refer to line numbers. The selection in LCR24 values is valid for the rest of the corresponding field. The upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). The relationship between LCR values and line numbers can be adjusted via VOFF8 to VOFF0, located in subaddresses 5BH (bit 4) and 5AH (bits 7 to 0) and FOFF subaddress 5BH (bit 7). The recommended values are VOFF[8:0] = 03H for 50 Hz sources (with FOFF = 0) and VOFF[8:0] = 06H for 60 Hz sources (with FOFF = 1), to accommodate line number conventions as used for PAL, SECAM and NTSC standards; see Tables 18 to 21.
The output interface block of the decoder part contains the ITU 656 formatter for the expansion port data output XPD7 to XPD0 (see Section 10.4.1) and the control circuit for the signals needed for the internal paths to the scaler and data slicer part. It also controls the selection of the reference signals for the RT port (RTCO, RTS0 and RTS1) and the expansion port (XRH, XRV and XDQ). The generation of the decoder data type control signals SET_RAW and SET VBI is also done within this block. These signals are decoded from the requested data type for the scaler input and/or the data slicer, selectable by the control registers LCR2 to LCR24; see Section 18.2.4.2. Table 17 Data formats at decoder output DATA TYPE NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DATA TYPE teletext EuroWST, CCST European Closed Caption
DECODER OUTPUT DATA FORMAT raw raw raw raw raw raw Y-CB-CR 4 : 2 : 2 raw raw raw raw raw raw raw raw Y-CB-CR 4 : 2 : 2
Video Programming Service (VPS) Wide screen signalling bits US teletext (WST) US Closed Caption (line 21) video component signal, VBI region CVBS data teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved US NABTS MOJI (Japanese) Japanese format switch (L20/22) video component signal, active video region
2004 Jun 29
51
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 18 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) LCR 521 259 522 260 523 active video 261 24 262 263 active video 524 525 1 264 2 265 2 3 266 3 4 267 4 5 serration pulses 268 5 269 6 serration pulses 6 7 270 7 8 271 8 9 272 9 equalization pulses equalization pulses equalization pulses equalization pulses 2004 Jun 29 52 Philips Semiconductors
HD-CODEC
Table 19 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2) Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) LCR 10 273 10 11 274 11 12 275 12 13 276 13 14 277 14 15 278 15 16 279 16 17 280 17 18 281 18 19 282 19 20 283 20 21 284 21 22 285 22 23 286 23 24 287 24 25 288 nominal VBI lines F1 nominal VBI lines F2 active video active video
Table 20 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1) Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 0 (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) LCR 621 309 622 active video 310 311 24 active video 623 624 312 625 313 1 314 serration pulses 2 2 serration pulses 315 316 3 3 4 317 4 5 equalization pulses equalization pulses equalization pulses
SAA7108AE; SAA7109AE
318 5
equalization pulses
Table 21 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 0 (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) LCR 6 319 6 7 320 7 8 321 8 9 322 9 10 323 10 11 324 11 12 325 12 13 326 13 14 327 14 15 328 15 16 329 16 17 330 17 18 331 18 19 332 19 20 333 20 21 334 21 22 335 22 23 336 23 24 337 24 25 338 nominal VBI lines F1 nominal VBI lines F2 active video active video
Product specification
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
ITU counting single field counting CVBS
622 309
623 310
624 311
625 312
1 1
2 2
3 3
4 4
5 5
6 6
7 7
... ...
22 22
23 23
HREF
F_ITU656
V123 (1) VSTO [8:0] = 134H VGATE
FID
(a) 1st field
VSTA [8:0] = 15H
ITU counting single field counting CVBS
309 309
310 310
311 311
312 312
313 313
314 1
315 2
316 3
317 4
318 5
319 6
... ...
335 22
336 23
HREF
F_ITU656 V123 (1) VSTO [8:0] = 134H VGATE
FID
(b) 2nd field
VSTA [8:0] = 15H
MHB540
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:
NAME HREF F_ITU656 V123 VGATE FID
RTS0 (PIN K13) X - X X X
RTS1 (PIN L10) X - X X X
XRH (PIN N2) X - - - -
XRV (PIN L5) - X X - -
For further information see programming section, Tables 171, 172 and 173.
Fig.30 Vertical timing diagram for 50 Hz/625 line systems.
2004 Jun 29
53
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
ITU counting single field counting CVBS
525 262
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
... ...
21 21
22 22
HREF
F_ITU656 V123 (1) VSTO [8:0] = 101H VGATE
FID
(a) 1st field
VSTA [8:0] = 011H
ITU counting single field counting CVBS
262 262
263 263
264 1
265 2
266 3
267 4
268 5
269 6
270 7
271 8
272 9
... ...
284 21
285 22
HREF
F_ITU656 V123 (1) VSTO [8:0] = 101H VGATE
FID
(b) 2nd field
VSTA [8:0] = 011H
MHB541
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:
NAME HREF F_ITU656 V123 VGATE FID
RTS0 (PIN K13 X - X X X
RTS1 (PIN L10) X - X X X
XRH (PIN N2) X - - - -
XRV (PIN L5) - X X - -
For further information see programming section, Tables 171, 172 and 173.
Fig.31 Vertical timing diagram for 60 Hz/525 line systems.
2004 Jun 29
54
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
CVBS input
burst processing delay ADC to expansion port: 140 x 1/LLC
expansion port data output
sync clipped
HREF (50 Hz) 720 x 2/LLC CREF CREF2 5 x 2/LLC HS (50 Hz) programming range 108 (step size: 8/LLC) 0 2 x 2/LLC -107 12 x 2/LLC 144 x 2/LLC
HREF (60 Hz) 16 x 2/LLC 720 x 2/LLC CREF CREF2 HS (60 Hz) programming range (step size: 8/LLC) 107 0 138 x 2/LLC
1 x 2/LLC 2 x 2/LLC -106
MHB542
The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Section 18.2.2.19 Tables 171 and 172); their polarity can be inverted via RTP0 and/or RTP1. The signals HREF and HS are available on pin XRH (see Section 18.2.2.20 Table 173).
Fig.32 Horizontal timing diagram (50/60 Hz).
2004 Jun 29
55
Philips Semiconductors
Product specification
HD-CODEC
9.3 Scaler
SAA7108AE; SAA7109AE
The overall H and V zooming (HV_zoom) is restricted by the input/output data rate relationships. With a safety margin of 2 % for running in and running out, the maximum HV_zoom is equal to: T_input_field - T_v_blanking 0.98 x ------------------------------------------------------------------------------------------------------------------------------------in_pixel x in_lines x out_cycle_per_pix x T_out_clk For example: 1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit data at 13.5 MHz data rate, 1 cycle per pixel; output: 8-bit data at 27 MHz, 2 cycles per pixel; the maximum HV_zoom is equal to: 20 ms - 24 x 64 s 0.98 x -------------------------------------------------------- = 1.18 720 x 288 x 2 x 37 ns 2. Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate (ITU 656), 2 cycles per pixel; output via I + H port: 16-bit data at 27 MHz clock, 1 cycle per pixel; the maximum HV_zoom is equal to: 16.666 ms - 22 x 64 s 0.98 x ------------------------------------------------------------- = 2.34 720 x 240 x 1 x 37 ns The video scaler receives its input signal from the video decoder or from the expansion port (X port). It gets 16-bit Y-CB-CR 4 : 2 : 2 input data at a continuous rate of 13.5 MHz from the decoder. A discontinuous data stream can be accepted from the expansion port, normally 8-bit wide ITU 656 like Y-CB-CR data, accompanied by a pixel qualifier on XDQ. The input data stream is sorted into two data paths, one for luminance (or raw samples), and one for time multiplexed chrominance CB and CR samples. A Y-CB-CR 4 : 1 : 1 input format is converted to 4 : 2 : 2 for the horizontal prescaling and vertical filter scaling operation. The scaler operation is defined by two programming pages A and B, representing two different tasks that can be applied field alternating or to define two regions in a field (e.g. with different scaling range, factors, and signal source during odd and even fields). Each programming page contains control for: * Signal source selection and formats * Task handling and trigger conditions * Input and output acquisition window definition * H prescaler, V scaler and H phase scaling. Raw VBI data will be handled as specific input format and need its own programming page (equals own task).
The High Performance video Scaler (HPS) is based on the system as implemented in the SAA7140, but enhanced in some aspects. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more flexible video stream timing at the image port, discontinuous transfers and handshake. The internal data flow from block to block is discontinuous dynamically, due to the scaling process. The flow is controlled by internal data valid and data request flags (internal handshake signalling) between the sub-blocks. Therefore the entire scaler acts as a pipeline buffer. Depending on the actually programmed scaling parameters the effective buffer can exceed to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced significantly. The high performance video scaler in the SAA7108AE; SAA7109AE has the following major blocks. * Acquisition control (horizontal and vertical timer) and task handling (the region/field/frame based processing) * Prescaler, for horizontal downscaling by an integer factor, combined with appropriate band limiting filters, especially anti-aliasing for CIF format * Brightness, saturation and contrast control for scaled output data * Line buffer, with asynchronous read and write, to support vertical upscaling (e.g. for videophone application, converting 240 into 288 lines, Y-CB-CR 4 : 2 : 2) * Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) for zoom and downscaling, or phase accurate Accumulation Mode (ACM) for large downscaling ratios and better anti-alias suppression * Variable Phase Delay (VPD), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square and rectangular pixel sampling * Output formatter for scaled Y-CB-CR 4 : 2 : 2, Y-CB-CR 4 : 1 : 1 and Y only (format also for raw data) * FIFO, 32-bit wide, with 64 pixel capacity in Y-CB-CR formats * Output interface, 8 or 16-bit (only if extended by H port) data pins wide, synchronous or asynchronous operation, with stream events on discrete pins, or coded in the data stream.
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Philips Semiconductors
Product specification
HD-CODEC
In VBI pass through operation the processing of prescaler and vertical scaling has to be disabled, however the horizontal fine scaling VPD can be activated. Upscaling (oversampling, zooming), free of frequency folding, up to factor 3.5 can be achieved, as required by some software data slicing algorithms. These raw samples are transported through the image port as valid data and can be output as Y only format. The lines are framed by SAV and EAV codes. 9.3.1 ACQUISITION CONTROL AND TASK HANDLING (SUBADDRESSES 80H, 90H, 91H, 94H TO 9FH AND C4H TO CFH)
SAA7108AE; SAA7109AE
9.3.1.1 Input field processing
The trigger event for the field sequence detection from external signals (X port) are defined in subaddress 92H. The state of the scalers horizontal reference signal at the time of the vertical reference edge is taken from the X port as field sequence identifier (FID). For example, if the falling edge of the XRV input signal is the reference and the state of XRH input is logic 0 at that time, the detected field ID is logic 0. The bits XFDV[92H[7]] and XFDH[92H[6]] define the detection event and state of the flag from the X port. For the default setting of XFDV and XFDH at `00' is taken from the state of the horizontal input at the falling edge of the vertical input. The scaler gets corresponding field ID information directly from the SAA7108AE; SAA7109AE decoder path. The FID flag is used to determine whether the first or second field of a frame is going to be processed within the scaler, and it is also used as trigger conditions for the task handling (see bits STRC[1:0] 90H[1:0]). According to ITU 656, FID at logic 0 means first field of a frame. To ease the application, the polarities of the detection results on the X port signals and the internal decoder ID can be changed via XFDH. As the V sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only recognises full lines, during 1st fields from the decoder the line count of the scaler can possibly shift by one line, compared to the 2nd field. This can be compensated for by switching the vertical trigger event, as defined by XDV0, to the opposite V sync edge or by using the vertical scalers phase offsets. The vertical timing of the decoder can be seen in Figs 30 and 31. As the horizontal and vertical reference events inside the ITU 656 data stream (from X port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently.
The acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the X port. The acquisition window is generated via pixel and line counters at the appropriate places in the data path. Only qualified pixels and lines (lines with qualified pixel) are counted from the X port. The acquisition window parameters are as follows: * Signal source selection: input video stream and formats from the decoder, or from the X port (programming bits SCSRC[1:0] 91H[5:4] and FSC[2:0] 91H[2:0]) Remark: The input of raw VBI data from the internal decoder should be controlled via the decoder output formatter and the LCR registers (see Section 9.2) * Vertical offset: defined in lines of the video source, parameter YO[11:0] 99H[3:0] 98H[7:0] * Vertical length: defined in lines of the video source, parameter YS[11:0] 9BH[3:0] 9AH[7:0] * Vertical length: defined in number of target lines, as a result of vertical scaling, parameter YD[11:0] 9FH[3:0] 9EH[7:0] * Horizontal offset: defined in number of pixels of the video source, parameter XO[11:0] 95H[3:0] 94H[7:0] * Horizontal length: defined in number of pixels of the video source, parameter XS[11:0] 97H[3:0] 96H[7:0] * Horizontal destination size: defined in target pixels after fine scaling, parameter XD[11:0] 9DH[3:0] 9CH[7:0]. The source start offset XO(11:0) and YO(11:0) opens the acquisition window, and the target size (XD11 to XD0, YD11 to YD0) closes the window, however the window is cut vertically if there are less output lines than required. The trigger events for the pixel and line counts are the horizontal and vertical reference edges as defined in subaddress 92H. The task handling is controlled by subaddress 90H; see Section 9.3.1.2. 2004 Jun 29 57
Philips Semiconductors
Product specification
HD-CODEC
Table 22 Processing trigger and start XDV1 92H[5] XDV0 92H[4] XDH 92H[2]
SAA7108AE; SAA7109AE
DESCRIPTION Internal decoder: The processing triggers at the falling edge of the V123 pulse (see Figs 30 (50 Hz) and 31 (60 Hz)), and starts earliest with the rising edge of the decoder HREF at line number:
0 0 0
1 0 0
0 0 0
4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count) 2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count) External ITU 656 stream: The processing starts earliest with SAV at line number 23 (50 Hz system), respectively line 20 (60 Hz system) (according ITU 656 count) Remarks: * To activate a task, the start condition must be fulfilled and the acquisition window offsets must be reached. For example, in case of `start immediately', and two regions are defined for one field, the offset of the lower region must be greater than (offset + length) of the upper region, if not, the actual counted H and V position at the end of the upper task is beyond the programmed offsets and the processing will `wait for next V'. * Basically, the trigger conditions are checked when a task is activated. It is important to know that they are not checked while a task is inactive. So it is not possible to trigger to the next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task A STRC[2:0] = 2, YO[11:0] = 310 and task B STRC[2:0] = 3, YO[11:0] = 310 results in an output field rate of 503 Hz). * After power-on or software reset (via SWRST[88H[5]]) task B gets priority over task A.
9.3.1.2
Task handling
The task handler controls the switching between the two programming register sets. It is controlled by subaddresses 90H and C0H. A task is enabled via the global control bits TEA[80H[4]] and TEB[80H[5]]. The handler is then triggered by events which can be defined for each register set. In the event of a programming error the task handling and the complete scaler can be reset to the initial states by the software reset bit SWRST[88H[5]] being set to logic 0. A software reset must be done after programming especially if the programming registers, related acquisition window and scaler are reprogrammed while a task is active. The difference in the disabling/enabling of a task, which is evaluated at the end of a running task (when SWRST is set to logic 0) is that it sets the internal state machines directly to their idle states. The start condition for the handler is defined by bits STRC[1:0] 90H[1:0] and means: start immediately, wait for next V sync, next FID at logic 0 or next FID at logic 1. The FID is evaluated if the vertical and horizontal offsets are reached. With RPTSK[90H[2]] at logic 1 the actual running task is repeated (under the defined trigger conditions) before handing control over to the alternate task. To support field rate reduction, the handler is also enabled to skip fields (bits FSKP[2:0] 90H[5:3]) before executing the task. A TOGGLE flag is generated (used for the correct output field processing), which changes state at the beginning of a task every time a task is activated; examples are given in Section 9.3.1.3.
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Philips Semiconductors
Product specification
HD-CODEC
9.3.1.3 Output field processing
SAA7108AE; SAA7109AE
When OFIDC = 0, the scalers input field ID is available as output field ID on bit 6 of SAV and EAV, and respectively on pin IGP0 (IGP1), if the FID output is selected. When OFIDC[90H[6]] = 1, the TOGGLE information is available as output field ID on bit 6 of SAV and EAV, and respectively on pin IGP0 (IGP1) if the FID output is selected. Additionally bit 7 of SAV and EAV can be defined via CONLH[90H[7]]. When CONLH[90H[7]] = 0 (default) it sets bit 7 to logic 1; a logic 1 inverts the SAV/EAV bit 7. So it is possible to mark the output of both tasks by different SAV/EAV codes. This bit can also be seen as `task flag' on pins IGP0 (IGP1), if the TASK output is selected.
As a reference for the output field processing, two signals are available for the back-end hardware. These signals are the input field ID from the scaler source and a TOGGLE flag, which shows that an active task is used an odd (1, 3, 5...) or even (2, 4, 6...) number of times. Using a single or both tasks and reducing the field or frame rate with the task handling functionality, the TOGGLE information can be used to reconstruct an interlaced scaled picture at a reduced frame rate. The TOGGLE flag is not synchronized to the input field detection, as it is only dependent on the interpretation of this information by the external hardware i.e. whether the output of the scaler is processed correctly; see Section 9.3.3.
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This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 23 Example for field processing 2004 Jun 29 60 Philips Semiconductors
HD-CODEC
FIELD SEQUENCE FRAME/FIELD SUBJECT EXAMPLE 1(1) 1/1 Processed by task State of detected ITU 656 FID TOGGLE flag Bit 6 of SAV/EAV byte Required sequence conversion at the vertical scaler(8) Output(9) Notes 1. Single task every field; OFIDC = 0; subaddress 90H at 40H; TEB[80H[5]] = 0. 2. Tasks are used to scale to different output windows, priority on task B after SWRST. 3. Both tasks at 12 frame rate; OFIDC = 0; subaddresses 90H at 43H and C0H at 42H. 4. In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted. 5. Task B at 23 frame rate constructed from neighbouring motion phases; task A at 13 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 45H. 6. Task A and B at 13 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 49H. 7. State of prior field. 8. It is assumed that input/output FID = 0 (upper lines); UP = upper lines; LO = lower lines. 9. O = data output; NO = no output. A 0 1 0 UP UP O 1/2 A 1 0 1 LO LO O 2/1 A 0 1 0 UP UP O EXAMPLE 2(2)(3) 1/1 B 0 1 0 UP UP O 1/2 A 1 1 1 LO LO O 2/1 B 0 0 0 UP UP O 2/2 A 1 0 1 LO LO O 1/1 B 0 1 1 UP LO O EXAMPLE 3(2)(4)(5) 1/2 B 1 0 0 LO UP O 2/1 A 0 1 1 UP LO O 2/2 B 1 1 1 LO LO O 3/1 B 0 0 0 UP UP O 3/2 A 1 0 0 LO UP O 1/1 B 0 0(7) 0(7) UP UP NO EXAMPLE 4(2)(4)(6) 1/2 B 1 1 1 LO LO O 2/1 A 0 1 1 UP LO O 2/2 B 1 1(7) 1(7) LO LO NO 3/1 B 0 0 0 UP UP O 3/2 A 1 0 0 LO UP O
SAA7108AE; SAA7109AE
Product specification
Philips Semiconductors
Product specification
HD-CODEC
9.3.2 HORIZONTAL SCALING
SAA7108AE; SAA7109AE
* The bit XC2_1[A2H[3]], which defines the weighting of the incoming pixels during the averaging process - XC2_1 = 0 1 + 1...+ 1 + 1 - XC2_1 = 1 1 + 2...+ 2 + 1. The prescaler creates a prescale dependent FIR low-pass, with up to 64 + 7 filter taps. The parameter XACL[5:0] can be used to vary the low-pass characteristic for a given integer prescale of 1XPSC[5:0]. The user can therewith decide between signal bandwidth (sharpness impression) and alias. The equation for the XPSC[5:0] calculation is: Npix_in XPSC[5:0] = lower integer of ---------------------Npix_out Where: the range is 1 to 63 (value 0 is not allowed); Npix_in = number of input pixel, and Npix_out = number of desired output pixel over the complete horizontal scaler. The use of the prescaler results in a XACL[5:0] and XC2_1 dependent gain amplification. The amplification can be calculated according to the equation: DC gain = [(XACL[5:0] - XC2_1) + 1] x (XC2_1 + 1) It is recommended to use sequence lengths and weights, which results in a 2N DC gain amplification, as these amplitudes can be renormalized by the XDCG[2:0] 1 controlled ------ shifter of the prescaler. N 2 The renormalization range of XDCG[2:0] is 1, 12... down to 1128. Other amplifications have to be normalized by using the following BCS control circuitry. In these cases the prescaler has to be set to an overall gain 1, e.g. for an accumulation sequence of `1 + 1 + 1' (XACL[5:0] = 2 and XC2_1 = 0), XDCG[2:0] must be set to `010', which equals 14 and the BCS has to amplify the signal to 43 (SATN[7:0] and CONT[7:0] value = lower integer of 4 x 64). 3 The use of XACL[5:0] is XPSC[5:0] dependent. XACL[5:0] must be <2 x XPSC[5:0]. XACL[5:0] can be used to find a compromise between bandwidth (sharpness) and alias effects.
The overall horizontal scaling factor has to be split into a binary and a rational value according to the following output pixel equation: H scale ratio = ----------------------------input pixel 1 1024 H scale ratio = --------------------------- x -----------------------------XPSC[5:0] XSCY[12:0] where, the parameter of the prescaler XPSC[5:0] = 1 to 63 and the parameter of VPD phase interpolation XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical values). For example, 13.5 is split into 14 x 1.14286. The binary factor is processed by the prescaler, the arbitrary non-integer ratio is achieved via the variable phase delay VPD circuitry, called horizontal fine scaling. The latter calculates horizontally interpolated new samples with a 6-bit phase accuracy, which relates to less than 1 ns jitter for regular sampling schemes. Together the prescaler and fine scaler form the horizontal scaler of the SAA7108AE; SAA7109AE. Using the accumulation length function of the prescaler (XACL[5:0] A1H[5:0]), application and destination dependent (e.g. scale for display or for a compression machine), a compromise between visible bandwidth and alias suppression can be found.
9.3.2.1
Horizontal prescaler (subaddresses A0H to A7H and D0H to D7H)
The prescaling function consists of an FIR anti-alias filter stage and an integer prescaler, which together form an adaptive prescale dependent low-pass filter to balance the sharpness and aliasing effects. The FIR pre-filter stage implements different low-pass characteristics to reduce the anti-alias for downscales in the range of 1 to 12. A CIF optimized filter is built-in, which reduces artefacts for CIF output formats (to be used in combination with the prescaler set to 12 scale); see Table 24. The function of the prescaler is defined by: * An integer prescaling ratio XPSC[5:0] A0H[5:0] (equals 1 to 63), which covers the integer downscale range 1 to 163 * An averaging sequence length XACL[5:0] A1H[5:0] (equals 0 to 63); range 1 to 64 * A DC gain renormalization XDCG[2:0] A2H[2:0]; 1 down to 1128)
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Philips Semiconductors
Product specification
HD-CODEC
Remark: Due to bandwidth considerations XPSC[5:0] and XACL[5:0] can be chosen differently to the previously mentioned equations or Table 25, as the horizontal phase scaling is able to scale in the range from zooming up by factor 3 to downscaling by a factor of 10248191. Figs 35 and 36 show some frequency characteristics of the prescaler. Table 25 shows the recommended prescaler programming. Other programming, than given in Table 25, may result in better alias suppression, but the resulting DC gain amplification needs to be compensated by the BCS control, according to the equation: 2 CONT[7:0] = SATN[7:0] = lower integer of --------------------------------DC gain x 64 Where: 2XDCG[2:0] DC gain DC gain = (XC2_1 + 1) x XACL[5:0] + (1 - XC2_1). Table 24 FIR prefilter functions PFUV[1:0] A2H[7:6] PFY[1:0] A2H[5:4] 00 01 10 11 LUMINANCE FILTER COEFFICIENTS bypassed 121 -1 1 1.75 4.5 1.75 1 -1 12221
XDCG[2:0]
SAA7108AE; SAA7109AE
For example, if XACL[5:0] = 5, XC2_1 = 1, then DC gain = 10 and the required XDCG[2:0] = 4. The horizontal source acquisition timing and the prescaling ratio is identical for both the luminance and chrominance path, but the FIR filter settings can be defined differently in the two channels. Fade-in and fade-out of the filters is achieved by copying an original source sample each as first and last pixel after prescaling. Figs 33 and 34 show the frequency characteristics of the selectable FIR filters.
CHROMINANCE COEFFICIENTS bypassed 121 3 8 10 8 3 12221
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62
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
6 V 3 (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 (1) PFY[1:0] = 01. (2) PFY[1:0] = 10. (3) PFY[1:0] = 11. -42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
(3) (2) (1)
MHB543
0.45 f_sig/f_clock
0.5
Fig.33 Luminance prefilter characteristic.
6 V 3 (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 (1) PFUV[1:0] = 01. (2) PFUV[1:0] = 10. (3) PFUV[1:0] = 11. -42 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2
(2) (3) (1)
MHB544
0.225 0.25 f_sig/f_clock
Fig.34 Chrominance prefilter characteristic.
2004 Jun 29
63
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
6 V 3 (dB) 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 XC2_1 = 0; Zero's at 1 f = n x -----------------------XACL + 1 with XACL = (1), (2), (3), (4) or (5) -39 -42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
(5) (4) (3) (2) (1)
MHB545
0.45 f_sig/f_clock
0.5
Fig.35 Examples for prescaler filter characteristics: effect of increasing XACL[5:0].
6 V 3 (dB) 0 -3 -6 -9 -12 -15 -18 -21 (1) XC2_1 = 0 and XACL[5:0] = 1. (2) XC2_1 = 1 and XACL[5:0] = 2. (3) XC2_1 = 0 and XACL[5:0] = 3. (4) XC2_1 = 1 and XACL[5:0] = 4. (5) XC2_1 = 0 and XACL[5:0] = 7. (6) XC2_1 = 1 and XACL[5:0] = 8. -24 -27 -30 -33 -36 -39 -42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
(2) (6) (5) (4) (3)
MHB546
(1)
3 dB at 0.25 6 dB at 0.33
0.45 f_sig/f_clock
0.5
Fig.36 Examples for prescaler filter characteristics: setting XC2_1 = 1.
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Philips Semiconductors
Product specification
HD-CODEC
Table 25 Example of XACL[5:0] usage RECOMMENDED VALUES PRESCALE XPSC RATIO [5:0] FOR LOWER BANDWIDTH REQUIREMENTS XACL[5:0] 1
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 1 1 1 1 1 1 1
SAA7108AE; SAA7109AE
FOR HIGHER BANDWIDTH REQUIREMENTS XACL[5:0] 0 1 3 4 7 7 7 8
(1) 16
XC2_1 0 1 (1 2 1) x
1 (1) 4
XDCG[2:0] 0 2 3
1 (1) 8
XC2_1 0 0 (1 1) x 0
1 (1) 2
XDCG[2:0] 0 1 2
FIR PREFILTER PFY[1:0]/ PFUV[1:0] 0 to 2 0 to 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3
1 2 3 4 5 6 7 8 9 10 13 15 16 19 31 32 35
0 2 4 7 8 8 8 15 15 16 16 31 31 32 32 63 63
1 (1 2 2 2 1) x 0 (1 1 1 1 1 1 1 1) x 18(1) 1 (1 2 2 2 2 2 2 2 1) x 1 (1 2 2 2 2 2 2 2 1) x 1 (1 2 2 2 2 2 2 2 1) x 116(1) 0 0 1 1 0 0 1 1 1 1
1 (1) 16 1 (1) 16
(1 1 1 1) x 3 4 4 4 4
1
1 (1) 4
1 (1 2 2 2 1) x 18(1) 0 (1 1 1 1 1 1 1 1) x 0 (1 1 1 1 1 1 1 1) x 0 (1 1 1 1 1 1 1 1) x 18(1) 1 1 1 1 1 1 1 1 1 1
1 (1) 8 1 (1) 8
3 3 3 3 4
1 (1) 16
(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) x
(1 2 2 2 2 2 2 2 1) x 8 8
4 5
1 (1) 32
4 4
1 (1) 16
(1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) x 116(1)
10
(1 2 2 2 2 2 2 2 1) x 116(1) (1 2 2 2 2 2 2 2 1) x 16 16 16 32 32 32 63
(1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1) x
13 15 16 19 31 32 35
5 5 5 6 6 7 7
5 5 5 6 6 6 7
Note 1. Resulting FIR function.
2004 Jun 29
65
Philips Semiconductors
Product specification
HD-CODEC
9.3.2.2 Horizontal fine scaling (variable phase delay filter; subaddresses A8H to AFH and D8H to DFH) 9.3.3.1
SAA7108AE; SAA7109AE
Line FIFO buffer (subaddresses 91H, B4H and C1H, E4H)
The horizontal fine scaling (VPD) should operate at scaling ratios between 12 and 2 (0.8 and 1.6), but can also be used for direct scaling in the range from 17.999 to (theoretical) zoom 3.5 (restriction due to the internal data path architecture), without prescaler. In combination with the prescaler a compromise between sharpness impression and alias can be found, which is signal source and application dependent. For the luminance channel a filter structure with 10 taps is implemented, for the chrominance a filter with 4 taps. Luminance and chrominance scale increments (XSCY[12:0] A9H[4:0] A8H[7:0] and XSCC[12:0] ADH[4:0] ACH[7:0]) are defined independently, but must be set in a 2 : 1 relationship in the actual data path implementation. The phase offsets XPHY[7:0] AAH[7:0] and XPHC[7:0] AEH[7:0] can be used to shift the sample phases slightly. XPHY[7:0] and XPHC[7:0] covers the phase offset range 7.999T to 132T. The phase offsets should also be programmed in a 2 : 1 ratio. The underlying phase controlling DTO has a 13-bit resolution. According to the equations 1 Npix_in XSCY[12:0] = 1024 x --------------------------- x ---------------------- and XPSC[5:0] Npix_out XSCY[12:0] XSCC[12:0] = -----------------------------2 The VPD covers the scale range from 0.125 to zoom 3.5. The VPD acts equivalent to a polyphase filter with 64 possible phases. In combination with the prescaler, it is possible to get high accurate samples from a highly anti-aliased integer downscaled input picture. 9.3.3 VERTICAL SCALING
The line FIFO buffer is a dual ported RAM structure for 768 pixels, with asynchronous write and read access. The line buffer can be used for various functions, but not all functions may be available simultaneously. The line buffer can buffer a complete unscaled active video line or more than one shorter lines (only for non-mirror mode), for selective repetition for vertical zoom-up. For zooming up from 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry for calculation. For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling scheme (MPEG, video phone, Indeo YUV-9) to ITU like sampling scheme 4 : 2 : 2, the chrominance line buffer is read twice or four times, before being refilled again by the source. By means of the input acquisition window definition it has to be preserved, that the processing starts with a line containing luminance and chrominance information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits FSC[2:1] 91H[2:1] define the distance between the Y/C lines. In case of 4 : 2 : 2 and 4 : 1 : 1 FSC2 and FSC1 have to be set to `00'. The line buffer can also be used for mirroring, i.e. for flipping the image left to right, for the vanity picture in video phone application (bit YMIR[B4H[4]]). In mirror mode only one active prescaled line can be held in the FIFO at a time. The line buffer can be utilized as excessive pipeline buffer for discontinuous and variable rate transfer conditions at the expansion port or image port.
9.3.3.2
Vertical scaler (subaddresses B0H to BFH and E0H to EFH)
Vertical scaling of any ratio from 64 (theoretical zoom) to 163 (icon) can be applied. The vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different modes. These are the Linear Phase Interpolation (LPI) and Accumulation (ACM) modes, controlled by YMODE[B4H[0]].
The vertical scaler of the SAA7108AE; SAA7109AE decoder part consists of a line FIFO buffer for line repetition and the vertical scaler block, which implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64 down to icon size 164. The vertical scaler is located between the BCS and horizontal fine scaler, so that the BCS can be used to compensate for the DC gain amplification of the ACM mode (see Section 9.3.3.2) as the internal RAMs are only 8-bit wide.
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66
Philips Semiconductors
Product specification
HD-CODEC
* LPI mode: In the linear phase interpolation mode (YMODE = 0) two neighbouring lines of the source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line relative to the source lines. This linear interpolation has a 6-bit phase resolution, which equals 64 intra line phases. It interpolates between two consecutive input lines only. The LPI mode should be applied for scaling ratios around 1 (down to 12), it must be applied for vertical zooming. * ACM mode: The vertical Accumulation (ACM) mode (YMODE = 1) represents a vertical averaging window over multiple lines, sliding over the field. This mode also generates phase correct output lines. The averaging window length corresponds to the scaling ratio, resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts. ACM can be applied for downscales only from ratio 1 down to 164. ACM results in a scale dependent DC gain amplification, which has to be precorrected by the BCS control of the scaler part. The phase and scale controlling DTO calculates in 16-bit resolution, controlled by parameters YSCY[15:0] B1H[7:0] B0H[7:0] and YSCC[15:0] B3H[7:0] B2H[7:0], continuously over the entire filed. A start offset can be applied to the phase processing by means of the parameters YPY3[7:0] to YPY0[7:0] in BFH[7:0] to BCH[7:0] and YPC3[7:0] to YPC0[7:0] in BBH[7:0] to B8H[7:0]. The start phase covers the range of 25532 to 132 lines offset. By programming appropriate, opposite, vertical start phase values (subaddresses B8H to BFH and E8H to EFH) depending on odd/even field ID of the source video stream and A/B page cycle, frame ID conversion and field rate conversion are supported (i.e. de-interlacing, re-interlacing). Figs 37 and 38 and Tables 26 and 27 describe the use of the offsets. Remark: The vertical start phase, as well as the scaling ratio are defined independently for luminance and chrominance channels, but must be set to the same values in the actual implementation for accurate 4 : 2 : 2 output processing. The vertical processing communicates on its input side with the line FIFO buffer. The scale related equations are: * Scaling increment calculation for ACM and LPI mode, downscale and zoom: YSCY[15:0] and YSCC[15:0] Nline_in = lower integer of 1024 x ------------------------ Nline_out
SAA7108AE; SAA7109AE
* BCS value to compensate DC gain in ACM mode (contrast and saturation have to be set): CONT[7:0] A5H[7:0] respectively SATN[7:0] A6H[7:0] Nline_out = lower integer of ------------------------ x 64 , or Nline_in 1024 = lower integer of ------------------------------ x 64 YSCY[15:0]
9.3.3.3
Use of the vertical phase offsets
As shown in Section 9.3.1.3, the scaler processing may run randomly over the interlaced input sequence. Additionally the interpretation and timing between ITU 656 field ID and real-time detection by means of the state of H sync at the falling edge of V sync may result in different field ID interpretation. A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the interlaced input fields are processed, without regard to the actual scale at the starting point of operation (see Fig.37). The four events to be considered are illustrated in Fig.38. In Tables 26 and 27 PHO is a usable common phase offset. It should be noted that the equations in Fig.38 also produce an interpolated output for the unscaled case, as the geometrical reference position for all conversions is the position of the first line of the lower field; see Table 26. If there is no need for UP-LO and LO-UP conversion and the input field ID is the reference for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the 12 line phase shift (PHO + 16) that can be skipped; this case is given in Table 27. The SAA7108AE; SAA7109AE supports 4 phase offset registers per task and component (luminance and chrominance). The value of 20H represents a phase shift of one line. The registers are assigned to the following events; e.g. subaddresses B8H to BBH: * B8H: 00 = input field ID 0, task status bit 0 (toggle status, see Section 9.3.1.3) * B9H: 01 = input field ID 0, task status bit 1 * BAH: 10 = input field ID 1, task status bit 0 * BBH: 11 = input field ID 1, task status bit 1.
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67
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
Depending on the input signal (interlaced or non-interlaced) and the task processing (50 Hz or field reduced processing with one or two tasks, see examples in Section 9.3.1.3), other combinations may also be possible, but the basic equations are the same.
unscaled input field 1 field 2
scaled output, no phase offset field 1 field 2
scaled output, with phase offset field 1 field 2
correct scale dependent position
scale dependent start offset
mismatched vertical line distances
MHB547
Fig.37 Basic problem of interlaced vertical scaling (example: downscale 35).
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68
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth
field 1 upper B A
field 2 lower
field 1 case UP-UP
field 2 case LO-LO
field 1 case UP-LO
field 2 case LO-UP
C D
MHB548
1024 Offset = ------------ = 32 = 1 line shift 32 1 A = -- input line shift = 16 2 1 1 YSCY[15:0] B = -- input line shift + -- scale increment = ------------------------------ + 16 2 2 64
1 YSCY[15:0] C = -- scale increment = -----------------------------2 64 D = no offset = 0
Fig.38 Derivation of the phase related equations (example: interlace vertical scaling down to 35, with field conversion).
Table 26 Examples for vertical phase offset usage: global equations INPUT FIELD UNDER PROCESSING Upper input lines Upper input lines Lower input lines Lower input lines OUTPUT FIELD INTERPRETED AS upper output lines lower output lines upper output lines lower output lines USED ABBREVIATION UP-UP UP-LO LO-UP LO-LO EQUATION FOR PHASE OFFSET CALCULATION (DECIMAL VALUES) PHO + 16 YSCY[15:0] PHO + ------------------------------ + 16 64 PHO YSCY[15:0] PHO + -----------------------------64
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69
Philips Semiconductors
Product specification
HD-CODEC
Table 27 Vertical phase offset usage; assignment of the phase offsets DETECTED INPUT FIELD ID 0 = upper lines TASK STATUS BIT 0 VERTICAL PHASE OFFSET YPY0[7:0] and YPC0[7:0]
SAA7108AE; SAA7109AE
CASE
EQUATION TO BE USED
case 1(1) UP-UP (PHO) case 2(2) UP-UP case 3(3) UP-LO case 1 case 2 case 3 case 1 UP-UP (PHO) UP-LO UP-UP YSCY[15:0] LO-LO PHO + ------------------------------ - 16 64 LO-UP LO-LO YSCY[15:0] LO-LO PHO + ------------------------------ - 16 64 LO-LO LO-UP
0 = upper lines
1
YPY1[7:0] and YPC1[7:0]
1 = lower lines
0
YPY2[7:0] and YPC2[7:0]
case 2 case 3 1 = lower lines 1 YPY3[7:0] and YPC3[7:0] case 1
case 2 case 3 Notes
1. Case 1: OFIDC[90H[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper output lines. 2. Case 2: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output lines. 3. Case 3: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output lines. 9.4 VBI data decoder and capture (subaddresses 40H to 7FH) For lines 2 to 24 of a field, per VBI line, 1 of 16 standards can be selected (LCRxxx[41:57[7:0]]: 23 x 2 x 4-bit programming bits). The definition for line 24 is valid for the rest of the corresponding field, normally no text data (video data) should be selected there (LCR24 = FFH) to stop the activity of the VBI data slicer during active video. To adjust the slicers processing to the input signal source, there are offsets in the horizontal and vertical direction available (parameters HOFF[5B,59[2:0,7:0]], VOFF[5B,5A[4,7:0]] and FOFF[5B[7]]). In difference to the scalers counting, the slicers offsets define the position of the horizontal and vertical trigger events related to the processed video field. The trigger events are the falling edge of HREF and the falling edge of V123 from the decoder processing part. The relationship of these programming values to the input signal and the recommended values can be seen in Tables 18 to 21.
The SAA7108AE; SAA7109AE contains a versatile VBI data decoder. The implementation and programming model accords to the VBI data slicer the built-in multimedia video data acquisition circuit of the SAA5284. The circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them into bytes. The result is buffered into a dedicated VBI data FIFO with a capacity of 2 x 56 bytes (2 x 14 Dwords). The clock frequency, signal source, field frequency and accepted error count must be defined in subaddress 40H. The VBI data standards that are supported are given in Table 28.
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Philips Semiconductors
Product specification
HD-CODEC
Table 28 Data types supported by the data slicer block DATA TYPE NUMBER 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 US NABTS MOJI (Japanese) no sliced data transmitted (video data selected) Image port output formatter (subaddresses 84H to 87H) STANDARD TYPE teletext EuroWST, CCST European Closed Caption VPS wide screen signalling bits US teletext (WST) US Closed Caption (line 21) (video data selected) (raw data selected) teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) DATA RATE (Mbits/s) 6.9375 0.500 5 5 5.7272 0.503 5 5 6.9375 1.8125 1.7898 5 5.7272 5.7272 5
SAA7108AE; SAA7109AE
FRAMING CODE 27H 001 9951H 1E3C1FH 27H 001 none none programmable programmable programmable programmable programmable programmable none
FC WINDOW WST625 CC625 VPS WSS WST525 CC525 disable disable general text VITC625 VITC525 open NABTS open disable
HAM CHECK always
always
optional
optional
programmable (A7H) Japtext
Japanese format switch (L20/22) 5
9.5
The output interface consists of a FIFO for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the I port, and a decoding and multiplexing unit, which generates the 8 or 16-bit wide output data stream together with the accompanying reference and help information. The clock for the output interface can be derived from an internal clock, decoder, expansion port or an externally provided clock which is appropriate, for example, for the VGA and frame buffer. The clock can be up to 33 MHz. The scaler provides the following video related timing reference events (signals), which are available on pins as defined by subaddresses 84H and 85H: * Output field ID * Start and end of vertical active video range * Start and end of active video line * Data qualifier or gated clock * Actually activated programming page (if CONLH is used) * Threshold controlled FIFO filling flags (empty, full, filled) * Sliced data marker. 2004 Jun 29 71
The disconnected data stream at the scaler output is accompanied by a data valid flag (or data qualifier), or is transported via a gated clock. Clock cycles with invalid data on the I port data bus (including the HPD pins in 16-bit output mode) are marked with code 00H. The output interface also arbitrates the transfer between scaled video data and sliced text data over the I port output. The bits VITX1 and VITX0 (subaddress 86H) are used to control the arbitration. The serialization of the internal 32-bit Dwords to 8-bit or 16-bit output (optional), as well as the insertion of the extended ITU 656 codes (SAV/EAV for video data, ANC or SAV/EAV codes for sliced text data) are also done here. For handshaking with the VGA controller, or other memory or bus interface circuitry, programmable FIFO flags are provided; see Section 9.5.2.
Philips Semiconductors
Product specification
HD-CODEC
9.5.1 SCALER OUTPUT FORMATTER (SUBADDRESSES 93H AND C3H)
SAA7108AE; SAA7109AE
FSI[2:0] defines the horizontal packing of the data, FOI[1:0] defines how many Y only lines are expected before a Y/C line will be formatted. If FYSK is set to logic 0 preceding Y only lines will be skipped, and the output will always start with a Y/C line. Additionally the output formatter limits the amplitude range of the video data (controlled by ILLV[85H[5]]); see Table 31.
The output formatter organizes the packing into the output FIFO. The following formats are available: Y-CB-CR 4 : 2 : 2, Y-CB-CR 4 : 1 : 1, Y-CB-CR 4 : 2 : 0, Y-CB-CR 4 : 1 : 0, Y only (e.g. for raw samples). The formatting is controlled by FSI[2:0] 93H[2:0], FOI[1:0] 93H[4:3] and FYSK[93H[5]]. The data formats are defined on Dwords, or multiples thereof, and are similar to the video formats as recommended for PCI multimedia applications (see SAA7146A). Planar formats are not supported. Table 29 Byte stream for different output formats OUTPUT FORMAT Y-CB-CR 4 : 2 : 2 Y-CB-CR 4 : 1 : 1 Y only CB0 CB0 Y0 Y0 Y0 Y1 CR0 CR0 Y2
BYTE SEQUENCE FOR 8-BIT OUTPUT MODES Y1 Y1 Y3 CB2 CB4 Y4 Y2 Y2 Y5 CR2 CR4 Y6 Y3 Y3 Y7 CB4 Y4 Y8 Y4 Y5 Y9 CR4 Y6 Y10 Y5 Y7 Y11 CB6 CB8 Y12 Y6 Y8 Y13
Table 30 Explanation to Table 29 NAME CBn Yn CRn EXPLANATION CB (B - Y) colour difference component, pixel number n = 0, 2, 4 to 718 Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 CR (R - Y) colour difference component, pixel number n = 0, 2, 4 to 718
Table 31 Limiting range on I port LIMIT STEP ILLV[85H[5]] 0 1 VALID RANGE DECIMAL VALUE 1 to 254 8 to 247 HEXADECIMAL VALUE 01 to FE 08 to F7 SUPPRESSED CODES (HEXADECIMAL VALUE) LOWER RANGE 00 00 to 07 UPPER RANGE FF F8 to FF
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Philips Semiconductors
Product specification
HD-CODEC
9.5.2 VIDEO FIFO (SUBADDRESS 86H)
SAA7108AE; SAA7109AE
The decoded VBI data is collected in the dedicated VBI data FIFO. Once the capture of a line is completed, the FIFO can be streamed through the image port, preceded by a header, giving the line number and standard. The VBI data period can be signalled via the sliced data flag on pin IGP0 or IGP1. The decoded VBI data is lead by the ITU ancillary data header (DID[5:0] 5DH[5:0] at value <3EH) or by SAV/EAV codes selected by DID[5:0] at value 3EH or 3FH. IGP0 or IGP1 is set if the first byte of the ANC header is valid on the I port bus; it is reset if an SAV occurs. Therefore it may frame multiple lines of text data output, in case the video processing starts with a distance of several video lines to the region of text data. Valid sliced data from the text FIFO is available on the I port as long as the IGP0 or IGP1 flag is set and the data qualifier is active on pin IDQ. The decoded VBI data is presented in two different data formats, controlled by bit RECODE. RECODE = 1: values 00H and FFH will be recoded to even parity values 03H and FCH RECODE = 0: values 00H and FFH may occur in the data stream as detected. 9.5.4 VIDEO AND TEXT ARBITRATION (SUBADDRESS 86H)
The video FIFO at the scaler output contains 32 Dwords. That corresponds to 64 pixels in 16-bit Y-CB-CR 4 : 2 : 2 format. But as the entire scaler can act as a pipeline buffer, the actually available buffer capacity for the image port is much higher, and can exceed beyond a video line. The image port and the video FIFO, can operate with the video source clock (synchronous mode) or with an externally provided clock (asynchronous, and burst mode), as appropriate for the VGA controller or attached frame buffer. The video FIFO provides 4 internal flags, which report to what extent the FIFO is actually filled. These are: * The FIFO Almost Empty (FAE) flag * The FIFO Combined (FC) flag or FIFO filled, which is set at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark * The FIFO Almost Full (FAF) flag * The FIFO Overflow (FOVL) flag. The trigger levels for FAE and FAF are programmable by FFL[1:0] 86H[3:2] (16, 24, 28, full) and FEL[1:0] 86H[1:0] (16, 8, 4, empty). The state of this flag can be seen on pins IGP0 or IGP1. The pin mapping is defined by subaddresses 84H and 85H; see Section 10.5. 9.5.3 TEXT FIFO
The data of the terminal VBI data slicer is collected in the text FIFO before transmission over the I port is requested (normally before the video window starts) and partitioned into two FIFO sections. A complete line is fed into the FIFO before a data transfer is requested. So normally, one line of text data is ready for transfer while the next text line is collected. Thus sliced text data is delivered as a block of qualified data, without any qualification gaps in the byte stream of the I port.
Sliced text data and scaled video data are transferred over the same bus, the I port. The mixed transfer is controlled by an arbitration circuit. If the video data is transferred without any interrupt and the video FIFO does not need to buffer any output pixel, the text data is inserted after the end of a scaled video line, normally during the video blanking interval.
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Philips Semiconductors
Product specification
HD-CODEC
9.5.5 DATA STREAM CODING AND REFERENCE SIGNAL GENERATION (SUBADDRESSES 84H, 85H AND 93H)
SAA7108AE; SAA7109AE
If ITU 656 like codes are not required, they can be suppressed in the output stream. As a further option, it is possible to provide the scaler with an external gating signal on pin ITRDY. It is therefore possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length. The sketched reference signals and events can be mapped to the I port output pins IDQ, IGPH, IGPV, IGP0 and IGP1. The polarities of all the outputs can be modified to enable flexible use. The default polarity for the qualifier and reference signals is logic 1 (active). Table 32 shows the relevant and supported SAV and EAV coding.
As horizontal and vertical reference signals are logic 1, active gate signals are generated, which frame the transfer of the valid output data. Alternatively, the horizontal and vertical trigger pulses can be generated on the rising edges of the gates. Due to the dynamic FIFO behaviour of the complete scaler path, the output signal timing has no fixed timing relationship to the real-time input video stream. Thus fixed propagation delays, in terms of clock cycles, related to the analog input can not be defined. The data stream is accompanied by a data qualifier. Additionally invalid data cycles are marked with code 00H. Table 32 SAV/EAV codes on the I port
SAV/EAV CODES ON I PORT(1) (HEX) EVENT DESCRIPTION MSB(2) OF SAV/EAV BYTE = 0 MSB(2) OF SAV/EAV BYTE = 1 FIELD ID = 0 Next pixel is FIRST pixel of any active line Previous pixel was LAST pixel of any active line, but not the last Next pixel is FIRST pixel of any V-blanking line Previous pixel was LAST pixel of the last active line or of any V-blanking line No valid data, do not capture and do not increment pointer Notes 1. The leading byte sequence is: FFH-00H-00H. 2. The MSB of the SAV/EAV code byte is controlled by: a) Scaler output data: task A MSB = CONLH[90H[7]]; task B MSB = CONLH[C0H[7]]. b) VBI data slicer output data: DID[5:0] 5DH[5:0] = 3EH MSB = 1; DID[5:0] 5DH[5:0] = 3FH MSB = 0. 0E 13 FIELD ID = 1 49 54 FIELD ID = 0 80 9D FIELD ID = 1 C7 DA HREF = active; VREF = active HREF = inactive; VREF = active HREF = active; VREF = inactive HREF = inactive; VREF = inactive IDQ pin inactive COMMENT
25 38
62 7F
AB B6
EC F1
00
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...
Philips Semiconductors
HD-CODEC
invalid data or end of raw VBI line
timing reference code FF 00 00
internal header IDI1
sliced data IDI2 D1_3 D1_4 D2_1
and filling data
timing reference code BC FF 00 00 EAV
invalid data 00 00
...
FF 00
00 00
00 EAV
SAV SDID DC
...
DDC_3 DDC_4 CS
...
MHB549
D1_1 D1_2 ANC header 00 FF FF internal header DID SDID DC IDI1 sliced data IDI2 D1_3 D1_4 ... DDC_3 DDC_4 CS BC
ANC data output is only filled up to the Dword boundary 00 00
...
ANC header active for DID (subaddress 5DH) <3EH
Fig.39 Sliced data formats on the I port in 8-bit mode.
Table 33 Explanation to Fig.39 NAME SAV SDID 75 DC start of active data; see Table 34 sliced data identification: NEP(1), EP(2), SDID5 to SDID0, freely programmable via I2C-bus subaddress 5EH, bits 5 to 0, e. g. to be used as source identifier Dword count: NEP(1), EP(2), DC5 to DC0. DC describes the number of succeeding 32-bit words: * For SAV/EAV mode DC is fixed to 11 Dwords (byte value 4BH) * For ANC mode it is: DC = 14(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes according to the chosen text standard. Note that the number of valid bytes inside the stream can be seen in the BC byte. EXPLANATION
SAA7108AE; SAA7109AE
IDI1 IDI2 Dn_m DDC_4 CS BC EAV Notes
internal data identification 1: OP(3), FID (field 1 = 0, field 2 = 1), LineNumber8 to LineNumber3 = Dword 1 byte 1; see Table 34 internal data identification 2: OP(3), LineNumber2 to LineNumber0, DataType3 to DataType0 = Dword 1 byte 2; see Table 34 Dword number n, byte number m last Dword byte 4, note: for SAV/EAV framing DC is fixed to 0BH, missing data bytes are filled up; the fill value is A0H the check sum byte, the check sum is accumulated from the SAV (respectively DID) byte to the DDC_4 byte number of valid sliced bytes counted from the IDI1 byte end of active data; see Table 34
Product specification
1. Inverted EP (bit 7); for EP see note 2. 2. Even parity (bit 6) of bits 5 to 0. 3. Odd parity (bit 7) of bits 6 to 0.
Philips Semiconductors
Product specification
HD-CODEC
Table 34 Bytes stream of the data slicer NICK NAME DID, SAV, EAV COMMENT subaddress 5DH = 00H subaddress 5DH; bit 5 = 1 subaddress 5DH bit 5 = 3EH; note 5 subaddress 5DH bit 5 = 3FH; note 5 SDID DC(8) IDI1 IDI2 CS BC Notes 1. NEP = inverted EP (see note 2). 2. EP = Even Parity of bits 5 to 0. 3. FID = 0: field 1; FID = 1: field 2. check sum byte valid byte count programmable via subaddress 5EH BIT 7 NEP(1) NEP 1 0 NEP NEP OP(9) OP CS6 OP BIT 6 EP(2) EP FID(3) FID(3) EP EP(2) FID(3) LN2(10) CS6 0 BIT 5 0 0 V(6) V(6) BIT 4 1
SAA7108AE; SAA7109AE
BIT 3 0
BIT 2 FID(3)
BIT 1 I1(4)
BIT 0 I0(4)
D4[5DH] D3[5DH] D2[5DH] D1[5DH] D0[5DH] H(7) H(7) P3 P3 P2 P2 P1 P1 P0 P0
D5[5EH] D4[5EH] D3[5EH] D2[5EH] D1[5EH] D0[5EH] DC5 LN8(10) LN1(10) CS5 CNT5 DC4 LN7(10) LN0(10) CS4 CNT4 DC3 LN6(10) DT3(11) CS3 CNT3 DC2 LN5(10) DT2(11) CS2 CNT2 DC1 LN4(10) DT1(11) CS1 CNT1 DC0 LN3(10) DT0(11) CS0 CNT0
4. I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1: line 24 to end of field. 5. Subaddress 5DH at 3EH and 3FH are used for ITU 656 like SAV/EAV header generation; recommended value. 6. V = 0: active video; V = 1: blanking. 7. H = 0: start of line; H = 1: end of line. 8. DC = Data Count in Dwords according to the data type. 9. OP = Odd Parity of bits 6 to 0. 10. LN = Line Number. 11. DT = Data Type according to table.
2004 Jun 29
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Philips Semiconductors
Product specification
HD-CODEC
9.6 Audio clock generation (subaddresses 30H to 3FH)
SAA7108AE; SAA7109AE
* Audio master Clocks Per Field, ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0] according to the equation: audio frequency ACPF[17:0] = round ----------------------------------------- field frequency- * Audio master Clocks Nominal Increment, ACNI[21:0] 36H[5:0] 35H[7:0] 34H[7:0] according to the equation: audio frequency 23 ACNI[21:0] = round -------------------------------------------- x 2 crystal frequency See Table 35 for examples. Remark: For standard applications the synthesized audio clock AMCLK can be used directly as master clock and as input clock for port AMXCLK (short cut) to generate ASCLK and ALRCLK. For high-end applications it is recommended to use an external analog PLL circuit to enhance the performance of the generated audio clock.
The SAA7108AE; SAA7109AE incorporates the generation of a field-locked audio clock, as an auxiliary function for video capture. An audio sample clock, that is locked to the field frequency, ensures that there is always the same predefined number of audio samples associated with a field, or a set of fields. This ensures synchronous playback of audio and video after digital recording (e.g. capture to hard disk), MPEG or other compression or non-linear editing. 9.6.1 MASTER AUDIO CLOCK
The audio clock is synthesized from the same crystal frequency as the line-locked video clock is generated. The master audio clock is defined by the parameters:
Table 35 Programming examples for audio master clock generation CRYSTAL FREQUENCY (MHz) FIELD (Hz) ACPF DECIMAL HEX DECIMAL ACNI HEX
AMCLK = 256 x 48 kHz (12.288 MHz) 32.11 24.576 50 59.94 50 59.94 245760 205005 - - 225792 188348 225792 188348 3C000 320CD - - 37200 2DFBC 37200 2DFBC 3210190 3210190 - - 2949362 2949362 3853517 3853 517 30FBCE 30FBCE - - 2D00F2 2D00F2 3ACCCD 3ACCCD
AMCLK = 256 x 44.1 kHz (11.2896 MHz) 32.11 24.576 50 59.94 50 59.94
AMCLK = 256 x 32 kHz (8.192 MHz) 32.11 24.576 50 59.94 50 59.94 163840 136670 163840 136670 28000 215DE 28000 215DE 2140127 2140127 2796203 2796203 20A7DF 20A7DF 2AAAAB 2AAAAB
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Philips Semiconductors
Product specification
HD-CODEC
9.6.2 SIGNALS ASCLK AND ALRCLK
SAA7108AE; SAA7109AE
Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for channel-select. The frequencies of these signals are defined by the parameters: f AMXCLK f AMXCLK * SDIV[5:0] 38H[5:0] according to the equation: f ASCLK = ------------------------------------- SDIV[5:0] = ------------------- - 1 ( SDIV + 1 ) x 2 2f ASCLK f ASCLK f ASCLK * LRDIV[5:0] 39H[5:0] according to the equation: f ALRCLK = -------------------------- LRDIV[5:0] = ---------------------LRDIV x 2 2f ALRCLK See Table 36 for examples. Table 36 Programming examples for ASCLK/ALRCLK clock generation AMXCLK (MHz) 12.288 11.2896 8.192 9.6.3 ASCLK (kHz) 1536 768 1411.2 2822.4 1024 2048 SDIV DECIMAL 3 7 3 1 3 1 HEX 03 07 03 01 03 01 ALRCLK (kHz) 48 44.1 32 LRDIV DECIMAL 16 8 16 32 16 32 HEX 10 08 10 10 10 10
OTHER CONTROL SIGNALS
Further control signals are available to define reference clock edges and vertical references; see Table 37. Table 37 Control signals CONTROL SIGNAL APLL[3AH[3]] Audio PLL mode: 0: PLL closed 1: PLL open AMVR[3AH[2]] Audio Master clock Vertical Reference: 0: internal vertical reference 1: external vertical reference LRPH[3AH[1]] ALRCLK Phase: 0: invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK 1: do not invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK SCPH[3AH[0]] ASCLK Phase: 0: invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK 1: do not invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK DESCRIPTION
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Philips Semiconductors
Product specification
HD-CODEC
10 INPUT/OUTPUT INTERFACES AND PORTS OF DIGITAL VIDEO DECODER PART The SAA7108AE; SAA7109AE has 5 different I/O interfaces. These are: * Analog video input interface, for analog CVBS and/or Y and C input signals * Audio clock port * Digital real-time signal port (RT port) * Digital video expansion port (X port), for unscaled digital video input and output * Digital image port (I port) for scaled video data output and programming * Digital host port (H port) for extension of the image port or expansion port from 8 to 16-bit. Table 38 Analog pin description SYMBOL AI24 to AI21 AI12 and AI11 AOUT PIN P6, P7, P9 and P10 P11 and P13 M10 O I I I/O DESCRIPTION 10.1
SAA7108AE; SAA7109AE
Analog terminals
The SAA7108AE; SAA7109AE has 6 analog inputs AI21 to AI24, AI11 and AI12 (see Table 38) for composite video CVBS or S-video Y/C signal pairs. Additionally, there are two differential reference inputs, which must be connected to ground via a capacitor equivalent to the decoupling capacitors at the 6 inputs. There are no peripheral components required other than the decoupling capacitors and 18 /56 termination resistors, one set per connected input signal (see also application example in Fig.53). Two anti-alias filters are integrated, and self adjusting via the clock frequency. Clamp and gain control for the two ADCs are also integrated. An analog video output pin (AOUT) is provided for testing purposes.
BIT MODE3 to MODE0
analog video signal inputs, e.g. 2 CVBS signals and two Y/C pairs can be connected simultaneously analog video output, for test purposes analog reference pins for differential ADC operation
AOSL1 and AOSL0 -
AI1D and AI2D P12 and P8 10.2 Audio clock signals
The SAA7108AE; SAA7109AE also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow PLL. This ensures that the multimedia capture and compression processes always gather the same predefined number of samples per video frame. An audio master clock AMCLK and two divided clocks, ASCLK and ALRCLK, are generated; see Table 39. * ASCLK: can be used as audio serial clock * ALRCLK: audio left/right channel clock. The ratios are programmable; see Section 9.6. Table 39 Audio clock pin description SYMBOL AMCLK PIN K12 I/O O DESCRIPTION audio master clock output BIT ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0] and ACNI[21:0] 36H[5:0] 35H[7:0] 34H[7:0] -
AMXCLK
J12
I
external audio master clock input for the clock division circuit, can be directly connected to output AMCLK for standard applications serial audio clock output, can be synchronized to rising or falling edge of AMXCLK audio channel (left/right) clock output, can be synchronized to rising or falling edge of ASCLK
ASCLK ALRCLK
K14 J13
O O
SDIV[5:0] 38H[5:0] and SCPH[3AH[0]] LRDIV[5:0] 39H[5:0] and LRPH[3AH[1]]
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Philips Semiconductors
Product specification
HD-CODEC
10.3 Clock and real-time synchronization signals
SAA7108AE; SAA7109AE
The Line-Locked Clock (LLC) is the double pixel clock at a nominal 27 MHz. It is locked to the selected video input, generating baseband video pixels according to "ITU recommendation 601". In order to support interfacing circuits, a direct pixel clock LLC2 is also provided. The pins for line and field timing reference signals are RTCO, RTS1 and RTS0. Various real-time status information can be selected for the RTS pins. The signals are always available (output) and reflect the synchronization operation of the decoder part in the SAA7108AE; SAA7109AE. The function of the RTS1 and RTS0 pins can be defined by bits RTSE1[3:0] 12H[7:4] and RTSE0[3:0] 12H[3:0]; see Table 40.
A crystal accurate frequency reference is required for the generation of the line-locked video (pixel) clock LLC, and the frame-locked audio serial bit clock. An oscillator is built-in, for fundamental or 3rd-harmonic crystals. The supported crystal frequencies are 32.11 or 24.576 MHz (defined during reset by strapping pin ALRCLK). Alternatively pins XTALId and XTALIe can be driven from an external single-ended oscillator. The crystal oscillation can be propagated as clock to other ICs in the system via pin XTOUTd.
Table 40 Clock and real-time synchronization signals SYMBOL PIN I/O DESCRIPTION - - XTOUTE[14H[3]] - - - BIT
Crystal oscillator XTALId XTALOd XTOUTd P2 P3 P4 I O O input for crystal oscillator, or reference clock output of crystal oscillator reference (crystal) clock output drive (optional)
Real-time signals (RT port) LLC LLC2 RTCO M14 L14 L13 O O O line-locked clock; nominal 27 MHz, double pixel clock locked to the selected video input signal line-locked pixel clock; nominal 13.5 MHz real-time control output; transfers real-time status information supporting RTC level 3.1 (see external document "RTC Functional Description", available on request) real-time status information line 0; can be programmed to carry various real-time informations; see Table 171 real-time status information line 1; can be programmed to carry various real-time informations; see Table 172
RTS0 RTS1
K13 L10
O O
RTSE0[3:0] 12H[3:0] RTSE1[3:0] 12H[7:4]
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Philips Semiconductors
Product specification
HD-CODEC
10.4 Video expansion port (X port)
SAA7108AE; SAA7109AE
As output, these are direct copies of the decoder signals. The data transfers through the expansion port represent a single D1 port, with half duplex mode. The SAV and EAV codes may be inserted optionally for data input (controlled by bit XCODE[92H[3]]). The input/output direction is switched for complete fields only.
The expansion port is intended for transporting video streams of image data from other digital video circuits such as MPEG encoder/decoder and video phone codec, to the image port (I port); see Table 41. The expansion port consists of two groups of signals/pins: * 8-bit data, I/O, regular video components Y-CB-CR 4 : 2 : 2, i.e. CB-Y-CR-Y, byte serial, exceptionally raw video samples (e.g. ADC test). In input mode the data bus can be extended to 16-bit by pins HPD7 to HPD0. * Clock, synchronization and auxiliary signals, accompanying the data stream, I/O. Table 41 Signals dedicated to the expansion port SYMBOL XPD7 to XPD0 PIN K2, K3, L1 to L3, M1, M2 and N1 M3 I/O I/O
DESCRIPTION X port data: in output mode controlled by decoder section, for data format see Table 42; in input mode Y-CB-CR 4 : 2 : 2 serial input data or luminance part of a 16-bit Y-CB-CR 4 : 2 : 2 input clock at expansion port: if output, then copy of LLC; as input normally a double pixel clock of up to 32 MHz or a gated clock (clock gated with a qualifier) data valid flag of the expansion port input (qualifier): if output, then decoder (HREF and VGATE) gate (see Fig.32) data request flag = ready to receive, to work with optional buffer in external device, to prevent internal buffer overflow; second function: input related task flag A/B horizontal reference signal for the X port: as output: HREF or HS from the decoder (see Fig.32); as input: a reference edge for horizontal input timing and a polarity for input field ID detection can be defined vertical reference signal for the X port: as output: V123 or field ID from the decoder, see Figs 30 and 31; as input: a reference edge for vertical input timing and for input field ID detection can be defined port control: switches X port input to 3-state
BIT OFTS[2:0] 13H[2:0], 91H[7:0] and C1H[7:0]
XCLK
I/O
XCKS[92H[0]]
XDQ
M4
I/O
-
XRDY
N3
O
XRQT[83H[2]]
XRH
N2
I/O
XRHS[13H[6]], XFDH[92H[6]] and XDH[92H[2]]
XRV
L5
I/O
XRVS[1:0] 13H[5:4], XFDV[92H[7]] and XDV[1:0] 92H[5:4]
XTRI
K1
I
XPE[1:0] 83H[1:0]
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Philips Semiconductors
Product specification
HD-CODEC
10.4.1 X PORT CONFIGURED AS OUTPUT
SAA7108AE; SAA7109AE
* Raw samples (data types 0 to 5 and 7 to 14): CB-CR samples are similar to data type 6, but CVBS samples are transferred instead of processed luminance samples within the Y time slots. The amplitude and offset of the CVBS signal is programmable via RAWG7 to RAWG0 and RAWO7 to RAWO0, see Chapter 18, Tables 178 and 179. For nominal levels see Fig.27. The relationship of LCR programming to line numbers is described in Section 9.2; see Tables 18 to 21. The data type selections by LCR are overruled by setting OFTS2 = 1 (subaddress 13H bit 2). This setting is mainly intended for device production testing. The VPO-bus carries the upper or lower 8 bits of the two ADCs depending on the OFTS[1:0] 13H[1:0] settings; see Table 173. The output configuration is done via MODE[3:0] 02H[3:0] settings; see Table 155. If a Y/C mode is selected, the expansion port carries the multiplexed output signals of both ADCs, in CVBS mode the output of only one ADC. No timing reference codes are generated in this mode. Remark: The LSBs (bit 0) of the ADCs are also available on pin RTS0; see Table 171. The SAV/EAV timing reference codes define the start and end of valid data regions. The ITU-blanking code sequence `- 80 - 10 - 80 - 10 -...' is transmitted during the horizontal blanking period, between EAV and SAV. The position of the F bit is constant according to ITU 656; see Tables 44 and 45. The V bit can be generated in two different ways (see Tables 44 and 45) controlled via OFTS1 and OFTS0; see Table 173. F and V bits change synchronously with the EAV code.
If the data output is enabled at the expansion port, then the data stream from the decoder is present. The data format of the 8-bit data bus is dependent on the chosen data type which is selectable by the line control registers LCR2 to LCR24; see Table 17. In contrast to the image port, the sliced data format is not available on the expansion port. Instead, raw CVBS samples are always transferred if any sliced data type is selected. Details of some of the data types on the expansion port are as follows: * Active video: (data type 15) contains components Y-CB-CR 4 : 2 : 2 signal, 720 active pixels per line. The amplitude and offsets are programmable via DBRI7 to DBRI0, DCON7 to DCON0, DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and OFFV0. For nominal levels see Fig.26. * Test line: (data type 6) is similar to the active video format, with some constraints within the data processing: - adaptive chrominance comb filter, vertical filter (chrominance comb filter for NTSC standards, PAL phase error correction) within the chrominance processing are disabled - adaptive luminance comb filter, peaking and chrominance trap are bypassed within the luminance processing. This data type is defined for future enhancements. It can be activated for lines containing standard test signals within the vertical blanking period. Currently most sources do not contain test lines. For nominal levels see Fig.26.
Table 42 Data format on the expansion port BLANKING PERIOD ... 80 10 TIMING REFERENCE CODE (HEX)(1) 720 PIXELS Y-CB-CR 4 : 2 : 2 DATA(2) TIMING REFERENCE CODE (HEX)(1) BLANKING PERIOD 10 ...
FF 00 00 SAV CB0 Y0 CR0 Y1 CB2 Y2 ... CR718 Y719 FF 00 00 EAV 80
Notes 1. The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to `010'; see Table 173. In this event the code sequence is replaced by the standard `- 80 - 10 -' blanking values. 2. If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y samples are replaced by CVBS samples.
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Philips Semiconductors
Product specification
HD-CODEC
Table 43 SAV/EAV format on expansion port XPD7 to XPD0 BIT 7 1 field bit 1st field: F = 0 2nd field: F = 1 BIT 6 (F) BIT 5 (V) vertical blanking bit VBI: V = 1 active video: V = 0 format
SAA7108AE; SAA7109AE
BIT 4 (H) H = 0 in SAV format H = 1 in EAV format
BIT 3 BIT 2 BIT 1 BIT 0 (P3) (P2) (P1) (P0) reserved; evaluation not recommended (protection bits according to ITU 656)
for vertical timing see Tables 44 and 45 Table 44 525 lines/60 Hz vertical timing V LINE NUMBER 1 to 3 4 to 19 20 21 22 to 261 262 263 264 and 265 266 to 282 283 284 285 to 524 525 F (ITU 656) OFTS[2:0] = 000 (ITU 656) 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 OFTS[2:0] = 001 according to selected VGATE position type via VSTA and VSTO (subaddresses 15H to 17H); see Tables 175 to 177
Table 45 625 lines/50 Hz vertical timing V LINE NUMBER 1 to 22 23 24 to 309 310 311 and 312 313 to 335 336 337 to 622 623 624 and 625 F (ITU 656) OFTS[2:0] = 000 (ITU 656) 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 OFTS[1:0] = 10 according to selected VGATE position type via VSTA and VSTO (subaddresses 15H to 17H); see Tables 175 to 177
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Philips Semiconductors
Product specification
HD-CODEC
10.4.2 X PORT CONFIGURED AS INPUT
SAA7108AE; SAA7109AE
The data formats at the image port are defined in Dwords of 32 bits (4 bytes), such as the related FIFO structures. However, the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are used for chrominance data. The four bytes of the Dwords are serialized in words or bytes. The available formats are as follows: * Y-CB-CR 4 : 2 : 2 * Y-CB-CR 4 : 1 : 1 * Raw samples * Decoded VBI data. For handshaking with the receiving VGA controller, or other memory or bus interface circuitry, F, H and V reference signals and programmable FIFO flags are provided. The information is provided on pins IGP0, IGP1, IGPH and IGPV. The function on these pins is controlled via subaddresses 84H and 85H. VBI data is collected over an entire line in its own FIFO and transferred as an uninterrupted block of bytes. Decoded VBI data can be signed by the VBI flag on pins IGP0 and IGP1. Because scaled video data and decoded VBI data may come from different and asynchronous sources, an arbitration scheme is needed. Normally the VBI data slicer has priority. The image port consists of the pins and/or signals, as given in Table 46. For pin constrained applications, or interfaces, the relevant timing and data reference signals can also be encoded into the data stream. Therefore the corresponding pins do not need to be connected. The minimum image port configuration requires 9 pins only, i.e. 8 pins for data including codes, and 1 pin for clock or gated clock. The inserted codes are defined in close relationship to the ITU-R BT.656 (D1) recommendation, where possible.
If data input mode is selected at the expansion port, then the scaler can choose its input data stream from the on-chip video decoder, or from the expansion port (controlled by bit SCSRC[1:0] 91H[5:4]). Byte serial Y-CB-CR 4 : 2 : 2, or subsets for other sampling schemes, or raw samples from an external ADC may be input (see also bits FSC[2:0] 91H[2:0]). The input data stream must be accompanied by an external clock XCLK, qualifier XDQ and reference signals XRH and XRV. Instead of the reference signal, embedded SAV and EAV codes, according to ITU 656, can also be accepted. The protection bits are not evaluated. XRH and XRV carry the horizontal and vertical synchronization signals for the digital video stream through the expansion port. The field ID of the input video stream is carried in the phase (edge) of XRV and state of XRH, or directly as FS (frame sync, odd/even signal) on the XRV pin (controlled by XFDV[92H[7]], XFDH[92H[6]] and XDV[1:0] 92H[5:4]). The trigger events on XRH (rising/falling edge) and XRV (rising/falling both edges) for the scalers acquisition window are defined by XDV[1:0] 92H[5:4] and XDH[92H[2]]. The signal polarity of the qualifier can also be defined by bit XDQ[92H[1]]. As an alternative to the qualifier, the input clock can be applied to a gated clock (clock gated with a data qualifier, controlled by bit XCKS[92H[0]]). In this event, all input data will be qualified. 10.5 Image port (I port)
The image port transfers data from the scaler as well as from the VBI data slicer, if selected (maximum 33 MHz). The reference clock is available at the ICLK pin as an output or as an input (maximum 33 MHz). As an output, the ICLK is derived from the line-locked decoder or expansion port input clock. The data stream from the scaler output is normally discontinuous. Therefore valid data during a clock cycle is accompanied by a data qualifying (data valid) flag on pin IDQ. For pin constrained applications the IDQ pin can be programmed to function as a gated clock output (bit ICKS2[80H[2]]).
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Philips Semiconductors
Product specification
HD-CODEC
The following deviations from "ITU 656 recommendation" are implemented at the SAA7108AE; SAA7109AEs image port interface: * SAV and EAV codes are only present in those lines, where data is to be transferred, i.e. active video lines, or VBI raw samples, no codes for empty lines * There may be more or less than 720 pixels between SAV and EAV * The data content and number of clock cycles during horizontal and vertical blanking is undefined, and may be not constant * The data stream may be interleaved with not-valid data codes, 00H, but SAV and EAV 4-byte codes are not interleaved with not-valid data codes * There may be an irregular pattern of not-valid data, or IDQ, and as a result, `CB - Y - CR - Y -' is not in a fixed phase to a regular clock divider
SAA7108AE; SAA7109AE
* VBI raw sample streams are enveloped with SAV and EAV, like normal video * Decoded VBI data is transported as Ancillary (ANC) data, two modes: - direct decoded VBI data bytes (8-bit) are directly placed in the ANC data field, 00H and FFH codes may appear in the data block (violation to ITU-R BT.656) - recoded VBI data bytes (8-bit) directly placed in ANC data field, 00H and FFH codes will be recoded to even parity codes 03H and FCH to suppress invalid ITU-R BT.656 codes. There are no empty cycles in the ancillary code or its data field. The data codes 00H and FFH are suppressed (changed to 01H or FEH respectively) in the active video stream, as well as in the VBI raw sample stream (VBI pass-through). As an option the number range can be limited further.
Table 46 Signals dedicated to the image port SYMBOL IPD7 to IPD0 PIN E14, D14, C14, B14, E13, D13, C13 and B13 H12 I/O I/O I port data DESCRIPTION BIT ICODE[93H[7]], ISWP[1:0] 85H[7:6] and IPE[1:0] 87H[1:0]
ICLK
I/O
continuous reference clock at image port, can be input or output, as output decoder LLC or XCLK from X port data valid flag at image port, qualifier, with programmable polarity; secondary function: gated clock
ICKS[1:0] 80H[1:0] and IPE[1:0] 87H[1:0] ICKS2[80H[2]], IDQP[85H[0]] and IPE[1:0] 87H[1:0]
IDQ
H14
O
IGPH
G12
O
horizontal reference output signal, copy of IDH[1:0] 84H[1:0], IRHP[85H[1]] and the horizontal gate signal of the scaler, with IPE[1:0] 87H[1:0] programmable polarity; alternative function: HRESET pulse vertical reference output signal, copy of the vertical gate signal of the scaler, with programmable polarity; alternative function: VRESET pulse general purpose output signal for I port general purpose output signal for I port target ready input signals port control, switches I port into 3-state IDV[1:0] 84H[3:2], IRVP[85H[2]] and IPE[1:0] 87H[1:0]
IGPV
F13
O
IGP1 IGP0 ITRDY ITRI
G13 F14 J14 G14
O O I I
IDG12[86H[4]], IDG1[1:0] 84H[5:4], IG1P[85H[3]] and IPE[1:0] 87H[1:0] IDG02[86H[5]], IDG0[1:0] 84H[7:6], IG0P[85H[4]] and IPE[1:0] 87H[1:0] - IPE[1:0] 87H[1:0]
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Philips Semiconductors
Product specification
HD-CODEC
10.6 Host port for 16-bit extension of video data I/O (H port)
SAA7108AE; SAA7109AE
The H port, pins HPD, can be used to extend the data I/O paths to 16-bit. The I port has functional priority. If I8_16[93H[6]] is set to logic 1 the output drivers of the H port are enabled and are dependent on the I port enable control. When I8_16 = 0, the HPD output is disabled. Table 47 Signals dedicated to the host port SYMBOL HPD7 to HPD0 10.7 10.7.1 PIN I/O DESCRIPTION BIT IPE[1:0] 87H[1:0], ITRI[8FH[6]] and I8_16[93H[6]]
A13, D12, C12, B12, I/O 16-bit extension for digital I/O A12, C11, B11 and A11 (chrominance component) 10.7.2
Basic input and output timing diagrams for the I and X ports I PORT OUTPUT TIMING
X PORT INPUT TIMING
The following diagrams (Figs 40 to 46) illustrate the output timing via the I port. IGPH and IGPV are indicated as logic 1 active gate signals. If reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates. Valid data is accompanied by the output data qualifier on pin IDQ. In addition, invalid cycles are marked with output code 00H. The IDQ output pin may be defined to be a gated clock output signal (ICLK AND internal IDQ).
The input timing requirements at the X port are the same as those for the I port output. However, the following differences should be noted: * It is not necessary to mark invalid cycles with a 00H code * No constraints on the input qualifier (can be a random pattern) * XCLK may by a gated clock (XCLK AND external XDQ). Remark: All timings illustrated are given for an uninterrupted output stream (no handshake with the external hardware).
ICLK
IDQ
IPD [ 7:0 ]
00
FF
00
00
SAV
00
CB
Y
CR
Y
00
CB
Y
CR
Y
00
IGPH
MHB550
Fig.40 Output timing at the I port for serial 8-bit data at start of a line (ICODE = 1).
2004 Jun 29
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
ICLK
IDQ
IPD [ 7:0 ]
00
CB
Y
CR
Y
00
CB
Y
CR
Y
00
IGPH
MHB551
Fig.41 Output timing at the I port for serial 8-bit data at start of a line (ICODE = 0).
ICLK
IDQ
IPD [ 7:0 ]
00
CB
Y
CR
Y
00
CB
Y
CR
Y
00
FF
00
00
EAV
00
IGPH
MHB552
Fig.42 Output timing at the I port for serial 8-bit data at end of a line (ICODE = 1).
2004 Jun 29
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
ICLK
IDQ
IPD [ 7:0 ]
00
CB
Y
CR
Y
00
CB
Y
CR
Y
00
IGPH
MHB553
Fig.43 Output timing at the I port for serial 8-bit data at end of a line (ICODE = 0).
ICLK
IDQ
IPD [ 7:0 ]
00
FF
00
00
Y0
Y1
00
Y2
Y3
Yn - 1
Yn
00
FF
00
00
HPD [ 7:0 ]
00
00
SAV
00
CB
CR
00
CB
CR
CB
CR
00
00
EAV
00
IGPH
MHB554
Fig.44 Output timing for 16-bit data output via the I and H port with codes (ICODE = 1), timing is like 8-bit output, but packages of 2 bytes per valid cycle.
2004 Jun 29
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth
IDQ
IGPH
IGPV
MHB555
Fig.45 Horizontal and vertical gate output timing.
handbook, full pagewidth
ICLK
IDQ
IPD [ 7:0 ]
00
00
FF
FF
DID
SDID
XX
YY
ZZ
CS
BC
00
00
00
HPD [ 7:0 ]
00
FF
00
00
SAV
BC
FF
00
00
EAV
sliced data flag on IGP0 or IGP1
MHB733
Fig.46 Output timing for sliced VBI data in 8-bit serial output mode (dotted graphs for SAV/EAV mode).
2004 Jun 29
89
Philips Semiconductors
Product specification
HD-CODEC
11 BOUNDARY SCAN TEST The SAA7108AE; SAA7109AE has built-in logic and 2 times 5 dedicated pins to support boundary scan testing, separately for the encoder and decoder part, which allows board testing without special hardware (nails). The SAA7108AE; SAA7109AE follows the "IEEE Std. 1149.1 Standard Test Access Port and Boundary-Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 10 special pins are Test Mode Select (TMSe and TMSd), Test Clock (TCKe and TCKd), Test Reset (TRSTe and TRSTd), Test Data Input (TDIe and TDId) and Test Data Output (TDOe and TDOd), where extension `e' refers to the encoder part and extension `d' refers to the decoder part. Table 48 BST instructions supported by the SAA7108AE; SAA7109AE INSTRUCTION BYPASS EXTEST SAMPLE DESCRIPTION
SAA7108AE; SAA7109AE
The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported; see Table 48. Details about the JTAG BST-TEST can be found in the specification "IEEE Std. 1149.1". Two files containing the detailed Boundary Scan Description Language (BSDL) of the SAA7108AE; SAA7109AE are available on request.
This mandatory instruction provides a minimum length serial path (1 bit) between TDIe (or TDId) and TDOe (or TDOd) when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. This optional instruction will provide information on the components manufacturer, part number and version number. This optional instruction allows testing of the internal logic (no support for customers available). This private instruction allows testing by the manufacturer (no support for customers available). is the possibility to check for the correct ICs mounted after production and to determine the version number of the ICs during field service. When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDIe (or TDId) and TDOe (or TDOd) of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller, this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDIe or TDId) and bit 0 is the least significant bit (nearest to TDOe or TDOd); see Fig.47.
CLAMP IDCODE INTEST USER1 11.1
Initialization of boundary scan circuit
The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRSTe or TRSTd pin LOW. 11.2 Device identification codes
A device identification register is specified in "IEEE Std. 1149.1b-1994". It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage 2004 Jun 29 90
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth
MSB 31 TDIe (or TDId) 28 27 0111000100000100 (0111000100010100) 16-bit part number 12 11 00000010101 1
LSB 0 1 TDOe (or TDOd)
nnnn
4-bit version code
11-bit manufacturer identification
MBL786
a. SAA7108AE.
handbook, full pagewidth
MSB 31 TDIe (or TDId) 28 27 0111000100000101 (0111000100010100) 16-bit part number 12 11 00000010101 1
LSB 0 1 TDOe (or TDOd)
nnnn
4-bit version code
11-bit manufacturer identification
MBL787
b. SAA7109AE. Fig.47 32 bits of identification code.
12 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and grounded (0 V); all supply pins connected together. SYMBOL VDDD VDDA Vi(A) Vi(n) Vi(D) PARAMETER digital supply voltage analog supply voltage input voltage at analog inputs input voltage at pins XTALI, SDA and SCL input voltage at digital inputs or I/O pins outputs in 3-state outputs in 3-state; note 1 VSS Tstg Tamb Vesd voltage difference between VSSA(n) and VSSD(n) storage temperature ambient temperature electrostatic discharge voltage CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 - -65 0 human body model; - note 2 machine model; note 3 Notes 1. Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < VDDD < 3.6 V. 2. Class 2 according to EIA/JESD22-114-B. 3. Class A according to EIA/JESD22-115-A. 2004 Jun 29 91 - MAX. +4.6 +4.6 +4.6 VDDD + 0.5 +4.6 +5.5 100 +150 70 2000 150 V V V V V V mV C C V V UNIT
Philips Semiconductors
Product specification
HD-CODEC
13 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Note PARAMETER thermal resistance from junction to ambient
SAA7108AE; SAA7109AE
CONDITIONS in free air
VALUE 32(1)
UNIT K/W
1. The overall Rth(j-a) value can vary depending on the board layout. To minimize the effective Rth(j-a) all power and ground pins must be connected to the power and ground layers directly. An ample copper area direct under the SAA7108AE; SAA7109AE with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the effective Rth(j-a). Please do not use any solder-stop varnish under the chip. In addition the usage of soldering glue with a high thermal conductance after curing is recommended. 14 CHARACTERISTICS OF THE DIGITAL VIDEO ENCODER PART Tamb = 0 to 70 C (typical values measured at Tamb = 25 C); unless otherwise specified. SYMBOL Supplies VDDA VDDIe VDD(DVO) analog supply voltage digital supply voltage digital supply voltage (DVO) 3.15 3.15 1.045 1.425 1.71 2.375 3.135 IDDA IDDD Inputs VIL LOW-level input voltage VDD(DVO) = 1.1 V, 1.5 V, 1.8 V or 2.5 V; note 3 VDD(DVO) = 3.3 V; note 3 pins RESe, TMSe, TCKe, TRSTe and TDIe VIH HIGH-level input voltage VDD(DVO) = 1.1 V, 1.5 V, 1.8 V or 2.5 V; note 3 VDD(DVO) = 3.3 V; note 3 pins RESe, TMSe, TCKe, TRSTe and TDIe ILI Ci input leakage current input capacitance clocks data I/Os at high-impedance -0.1 -0.5 -0.5 - - - +0.2 +0.8 +0.8 V V V analog supply current digital supply current note 1 note 2 1 1 3.3 3.3 1.1 1.5 1.8 2.5 3.3 110 175 3.45 3.45 1.155 1.575 1.89 2.625 3.465 115 200 V V V V V V V mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VDD(DVO) - 0.2 - 2 2 - - - - - - - - - -
VDD(DVO) + 0.1 V VDD(DVO) + 0.3 V VDDIe + 0.3 10 10 10 10 V A pF pF pF
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Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL Outputs VOL
PARAMETER
CONDITIONS
MIN.
TYP. - - -
MAX.
UNIT
LOW-level output voltage
VDD(DVO) = 1.1 V, 1.5 V, 1.8 V or 2.5 V; note 3 VDD(DVO) = 3.3 V; note 3 pins TDOe, TTXRQ_XCLKO2, VSM and HSM_CSYNC
0 0 0
0.1 0.4 0.4
V V V
VOH
HIGH-level output voltage VDD(DVO) = 1.1 V, 1.5 V, 1.8 V or 2.5 V; note 3 VDD(DVO) = 3.3 V; note 3 pins TDOe, TTXRQ_XCLKO2, VSM and HSM_CSYNC
VDD(DVO) - 0.1 - 2.4 2.4 - -
VDD(DVO) VDD(DVO) VDDIe
V V V
I2C-bus; pins SDAe and SCLe VIL VIH Ii VOL Io TPIXCLK td(CLKD) tr tf Input timing tSU;DAT tHD;DAT tSU;DAT tHD;DAT input data set-up time input data hold time input data set-up time input data hold time pins PD11 to PD0 pins PD11 to PD0 pins HSVGC, VSVGC and FSVGC; note 6 pins HSVGC, VSVGC and FSVGC; note 6 2 0.9 2 1.5 - - - - - - - - ns ns ns ns LOW-level input voltage HIGH-level input voltage input current LOW-level output voltage (pin SDAe) output current Vi = LOW or HIGH IOL = 3 mA during acknowledge -0.5 0.7VDDIe -10 - 3 - - - - - - - 50 50 - - 0.3VDDIe VDDIe + 0.3 +10 0.4 - - - 60 60 1.5 1.5 V V A V mA
Clock timing; pins PIXCLKI and PIXCLKO cycle time delay from PIXCLKO to PIXCLKI duty factor tHIGH/TPIXCLK duty factor tHIGH/TCLKO2 rise time fall time note 4 note 5 note 4 output note 4 note 4 12 - 40 40 - - ns ns % % ns ns
Crystal oscillator fnom f/fnom nominal frequency permissible deviation of nominal frequency note 7 - -50 27 - - +50 MHz 10-6
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - - - 1.5 3.5
MAX.
UNIT C pF fF pF
CRYSTAL SPECIFICATION Tamb CL RS C1 C0 ambient temperature load capacitance series resistance motional capacitance (typical) parallel capacitance (typical) 0 8 - 1.2 2.8 70 - 80 1.8 4.2
Data and reference signal output timing CL to(h)(gfx) to(d)(gfx) to(h) output load capacitance output hold time to graphics controller output delay time to graphics controller output hold time pins HSVGC, VSVGC, FSVGC and CBO pins HSVGC, VSVGC, FSVGC and CBO pins TDOe, TTXRQ_XCLKO2, VSM and HSM_CSYNC pins TDOe, TTXRQ_XCLKO2, VSM and HSM_CSYNC 8 1.5 - 3 - - - - 40 - 10 - pF ns ns ns
to(d)
output delay time
-
-
25
ns
CVBS and RGB outputs Vo(CVBS)(p-p) output voltage CVBS (peak-to-peak value) Vo(VBS)(p-p) output voltage VBS (S-video) (peak-to-peak value) output voltage C (S-video) (peak-to-peak value) output voltage R, G, B (peak-to-peak value) inequality of output signal voltages output load resistance output signal bandwidth of DACs low frequency integral linearity error of DACs low frequency differential linearity error of DACs -3 dB; note 8 see Table 49 see Table 49 - - 1.23 1 - - V V
Vo(C)(p-p)
see Table 49
-
0.89
-
V
Vo(RGB)(p-p) Vo RL BDAC ILElf(DAC) DLElf(DAC)
see Table 49
- - - - - -
0.7 2 37.5 170 - -
- - - - 3 1
V % MHz LSB LSB
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Product specification
HD-CODEC
Notes 1. Minimum value for I2C-bus bit DOWNA = 1. 2. Minimum value for I2C-bus bit DOWND = 1.
SAA7108AE; SAA7109AE
3. Levels refer to pins PD11 to PD0, FSVGC, PIXCLKI, VSVGC, PIXCLKO, CBO, TVD, and HSVGC, being inputs or outputs directly connected to a graphics controller. Input sensitivity is 1/2VDD(DVO) + 100 mV for HIGH and 1/2VDD(DVO) - 100 mV for LOW. The reference voltage 1/2VDD(DVO) is generated on chip. 4. The data is for both input and output direction. 5. This parameter is arbitrary, if PIXCLKI is looped through the VGC. 6. Tested with programming IFBP = 1. 7. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 8. 1 B -3 dB = ---------------------------------------------------------- with Cext = 20 pF (typical). 2 ( R o(L) ( C ext + 5 pF ) )
15 CHARACTERISTICS OF THE DIGITAL VIDEO DECODER PART VDDD = 3.0 to 3.6 V; VDDA = 3.1 to 3.5 V; Tamb = 0 to 70 C (typical values measured at Tamb = 25 C); timings and levels refer to drawings and conditions illustrated in Fig.52; unless otherwise specified. SYMBOL Supplies VDDD IDDD PD VDDA IDDA digital supply voltage digital supply current power dissipation digital part analog supply voltage analog supply current AOSL1 and AOSL0 = 0 CVBS mode Y/C mode PA Ptot(A+D) Ptot(A+D)(pd) power dissipation analog part total power dissipation analog and digital part total power dissipation analog and digital part in Power-down mode total power dissipation analog and digital part in power-save mode CVBS mode Y/C mode CVBS mode Y/C mode CE pulled down to ground - - - - - - - 47 72 150 240 450 540 5 - - - - - - - mA mA mW mW mW mW mW X port 3-state; 8-bit I port 3.15 - - 3.15 3.3 90 300 3.3 3.45 - - 3.45 V mA mW V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Ptot(A+D)(ps)
I2C-bus controlled via address 88H = 0FH
-
75
-
mW
Analog part Iclamp clamping current VI = 0.9 V DC - 8 - A
2004 Jun 29
95
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL Vi(p-p)
PARAMETER input voltage (peak-to-peak value)
CONDITIONS for normal video levels - 1 V (p-p), -3 dB termination 27/47 and AC coupling required; coupling capacitor = 22 nF clamping current off fi < 5 MHz at -3 dB
MIN.
TYP. 0.7 -
MAX.
UNIT V
Zi Ci cs B diff
input impedance input capacitance channel crosstalk
200 - - - -
- - - 7 2
- 10 -50 - -
k pF dB
9-bit analog-to-digital converters analog bandwidth differential phase (amplifier plus anti-alias filter bypassed) differential gain (amplifier plus anti-alias filter bypassed) ADC clock frequency DC differential linearity error DC integral linearity error MHz deg
Gdiff
-
2
-
%
fclk(ADC) DLEdc(d) ILEdc(i) Digital inputs
12.8 - - -0.5 0.7VDDD -0.3 2.0 -0.3 2.0 - - I/O at high-impedance - - -0.5 2.4
- 0.7 1 - - - - - - - - - - - -
14.3 - - +0.3VDDD VDDD + 0.5 +0.8 VDDD + 0.3 +0.8 5.5 1 10 8
MHz LSB LSB
VIL(SDAd,SCLd) LOW-level input voltage pins SDAd and SCLd VIH(SDAd,SCLd) HIGH-level input voltage pins SDAd and SCLd VIL(XTALId) VIH(XTALId) VIL(n) VIH(n) ILI ILI/O Ci VOL(SDAd) VOL(clk) VOH(clk) LOW-level CMOS input voltage pin XTALId HIGH-level CMOS input voltage pin XTALId LOW-level input voltage all other inputs HIGH-level input voltage all other inputs input leakage current I/O leakage current input capacitance
V V V V V V A A pF
Digital outputs; note 1 LOW-level output voltage pin SDAd LOW-level output voltage for clocks HIGH-level output voltage for clocks SDAd at 3 mA sink current 0.4 +0.6 VDDD + 0.5 V V V
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL VOL VOH
PARAMETER LOW-level output voltage all other digital outputs HIGH-level output voltage all other digital outputs
CONDITIONS 0
MIN. - -
TYP.
MAX. 0.4 VDDD + 0.5
UNIT V V
2.4
Clock output timing (LLC and LLC2); note 2 CL(LLC) Tcy tr tf td(LLC-LLC2) output load capacitance cycle time duty factors for tLLCH/tLLC and tLLC2H/tLLC2 rise time LLC and LLC2 fall time LLC and LLC2 delay time between LLC and LLC2 output pin LLC pin LLC2 CL = 40 pF 0.2 V to VDDD - 0.2 V VDDD - 0.2 V to 0.2 V measured at 1.5 V; CL = 25 pF 50 Hz field 60 Hz field fH/fH(nom) fsc(nom) permissible static deviation Subcarrier PLL nominal subcarrier frequency PAL BGHI NTSC M PAL M PAL N fsc fxtal(nom) fxtal(nom) fxtal(nom)(T) lock-in range Crystal oscillator for 32.11 MHz; note 3 nominal frequency permissible nominal frequency deviation permissible nominal frequency deviation with temperature 3rd-harmonic - - - 32.11 - - - 70 x 10-6 MHz - - - - 400 4433619 3579545 3575612 3582056 - - - - - - Hz Hz Hz Hz Hz 15 35 70 40 - - -4 - - - - - - - 50 39 78 60 5 5 +8 pF ns ns % ns ns ns
Horizontal PLL fH(nom) nominal line frequency - - - 15625 15734 - - - 5.7 Hz Hz %
30 x 10-6
CRYSTAL SPECIFICATION (X1) Tamb(X1) CL Rs C1 C0 fxtal(nom) fxtal(nom) ambient temperature load capacitance series resonance resistor motional capacitance parallel capacitance 0 8 - - - 3rd-harmonic - - - - 40 70 - 80 C pF fF pF
1.5 20 % - 4.3 20 % - 24.576 - - 50 x 10-6
Crystal oscillator for 24.576 MHz; note 3 nominal frequency permissible nominal frequency deviation 97 MHz
2004 Jun 29
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL fxtal(nom)(T)
PARAMETER permissible nominal frequency deviation with temperature
CONDITIONS -
MIN. -
TYP.
MAX. 20 x 10-6
UNIT
CRYSTAL SPECIFICATION (X1) Tamb(X1) CL Rs C1 C0 Tcy tr tf tSU;DAT tHD;DAT CL Tcy tr tf ambient temperature load capacitance series resonance resistor motional capacitance parallel capacitance 0 8 - - - 31 40 - - - - 15 35 35 0.6 to 2.6 V 2.6 to 0.6 V - - - - 40 70 - 80 C pF fF pF
1.5 20 % - 3.5 20 % - - 50 - - 10 3 - - - - - 45 60 5 5 - - 50 39 65 5 5
Clock input timing (XCLK) cycle time duty factors for tLLCH/tLLC rise time fall time ns % ns ns
Data and control signal input timing X port, related to XCLK input input data set-up time input data hold time ns ns
Clock output timing output load capacitance cycle time duty factors for tXCLKH/tXCLKL rise time fall time pF ns % ns ns
Data and control signal output timing X port, related to XCLK output (for XPCK[1:0] 83H[5:4] = 00 is default); note 2 CL tOHD;DAT tPD output load capacitance output hold time propagation delay from positive edge of XCLK output CL = 15 pF CL = 15 pF 15 - - - 14 24 50 - - pF ns ns
Control signal output timing RT port, related to LLC output CL tOHD;DAT tPD output load capacitance output hold time propagation delay from positive edge of LLC output CL = 15 pF CL = 15 pF 15 - - - 14 24 50 - - pF ns ns
ICLK output timing CL Tcy 2004 Jun 29 output load capacitance cycle time duty factors for tICLKH/tICLKL 98 15 31 35 - - - 50 45 65 pF ns %
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL tr tf CL tOHD;DAT to(d) Tcy Notes
PARAMETER rise time fall time
CONDITIONS 0.6 to 2.6 V 2.6 to 0.6 V - - 15 CL = 15 pF CL = 15 pF - - 31
MIN. - - - 12 22 -
TYP. 5 5
MAX.
UNIT ns ns
Data and control signal output timing I port, related to ICLK output (for IPCK[1:0] 87H[5:4] = 00 is default) output load capacitance at all outputs output data hold time output delay time 50 - - 100 pF ns ns
ICLK input timing cycle time ns
1. The levels must be measured with load circuits; 1.2 k at 3 V (TTL load); CL = 50 pF. 2. The effects of rise and fall times are included in the calculation of tOHD;DAT and tPD. Timings and levels refer to drawings and conditions illustrated in Fig.52. 3. The crystal oscillator drive level is 0.28 mW (typ.). 16 TIMING 16.1 Digital video encoder part
handbook, full pagewidth
TPIXCLK tHIGH VOH 0.5VDD(DVO) VOL td(CLKD) tf tr VIH
PIXCLKO
PIXCLKI
0.5VDD(DVO) VIL tHD;DAT tSU;DAT tHD;DAT tSU;DAT VIH
PDn VIL to(d) to(h) any output VOL
MBL789
VOH
Fig.48 Input/output timing specification.
2004 Jun 29
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth
HSVGC
CBO
PD XOFS IDEL XPIX HLEN
MHB905
Fig.49 Horizontal input timing.
handbook, full pagewidth
HSVGC
VSVGC
CBO YOFS YPIX
MHB906
Fig.50 Vertical input timing.
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Philips Semiconductors
Product specification
HD-CODEC
16.1.1 TELETEXT TIMING
SAA7108AE; SAA7109AE
Time ti(TTXW) is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s (world standard TTX) or 288 teletext bits at a text data rate of 5.7272 Mbits/s (NABTS). The insertion window is not opened if the control bit TTXEN is zero. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion. It is essential to note that the two pins used for teletext insertion must be configured for this purpose by the correct I2C-bus register settings.
Time tFD is the time needed to interpolate input data TTX and insert it into the CVBS and VBS output signal, such that it appears at tTTX = 9.78 s (PAL) or tTTX = 10.5 s (NTSC) after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ_XCLKO2 in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH state at output pin TTXRQ_XCLKO2, a new teletext bit must be provided by the source. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse.
handbook, full pagewidth
CVBS/Y t TTX text bit #: TTX_SRES t PD TTXRQ_XCLKO2
MHB891
t i(TTXW) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
t FD
Fig.51 Teletext timing.
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Philips Semiconductors
Product specification
HD-CODEC
16.2 Digital video decoder part
SAA7108AE; SAA7109AE
handbook, full pagewidth
Tcy t XCLKH 2.4 V clock input XCLK 1.5 V 0.6 V t SU;DAT t HD;DAT tf tr
data and control inputs (X port)
2.0 V not valid 0.8 V t SU;DAT t HD;DAT 2.0 V
input XDQ 0.8 V t o(d) t OHD;DAT data and control outputs X port, I port -2.4 V -0.6 V t X(I)CLKH clock outputs LLC, LLC2, XCLK, ICLK and ICLK input t X(I)CLKL -2.6 V -1.5 V -0.6 V tf tr
MHB735
Fig.52 Data input/output timing diagram (X port, RT port and I port).
2004 Jun 29
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Philips Semiconductors
Product specification
HD-CODEC
17 APPLICATION INFORMATION
VDD(EL9) VDD(EL7) VDD(EG11) VDD(ED10) VDD(AM8) VDD(AM9) VDD(AN11)
SAA7108AE; SAA7109AE
handbook, full pagewidth
VDD(ID11) VDD(IF11) VDD(IJ4) VDD(IJ11) VDD(IL4) VDD(IL11) VDD(XL8)
D10 G11 L7 L9
N11 M9 M8
D11 F11 J4 J11 L4 L11
E12 F12
L8
R27 0 L12 M11 K2 K3 L1 L2 L3 M1 M2 N1 K1 L5 N2 M3 M4 N3 A13 D12 C12 B12 A12 C11 B11 A11 E14 D14 C14 B14 E13 D13 C13 B13 G14 F13 G12 G13 F14 H12 H14 J14 J12 J13 K14 K12 L10 K13 L13 L14 M14 M12 N14 M5 M6 N4 N6 N5 J2 J1 J3 C10 B10 H13 P4 P3 P2 L34 10 H C107 1 nF R49 C103 10 pF BSC0 BSC1 BSC2 XPD7 XPD6 XPD5 XPD4 XPD3 XPD2 XPD1 XPD0 XPCON5 XPCON4 XPCON3 XPCON2 XPCON1 XPCON0 HPD7 HPD6 HPD5 HPD4 HPD3 HPD2 HPD1 HPD0 IPD7 IPD6 IPD5 IPD4 IPD3 IPD2 IPD1 IPD0 IPCON7 IPCON6 IPCON5 IPCON4 IPCON3 IPCON2 IPCON1 IPCON0 AUDIO3 AUDIO2 AUDIO1 AUDIO0 RCON2 RCON1 RCON0 R37 33 R38 33 LLC2 LLC RES R47 open TMSd TCLKd TRSTd TDId TDOd TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 VDDP R28 0 SDA SCL
VDDId VDDId
VDDId VDDId
VDDAd VDDAd
VDDAd
VDDEd VDDEd
VDDEd VDDEd
VDDId VDDId
VDDXd
n.c. TVD
SDAd SCLd XPD7 XPD6 XPD5 XPD4 XPD3 XPD2 XPD1 XPD0 XTRI XRV XRH XCLK XDQ XRDY HPD7 HPD6 HPD5 HPD4 HPD3 HPD2 HPD1 HPD0 IPD7 IPD6 IPD5 IPD4 IPD3 IPD2 IPD1 IPD0
XPD[0:7]
32.11 MHz VDDP AUDIO2 R12 4.7 k
24.576 MHz DGND JP43 fXTAL 'strapping'
I2C-BUS_Adr:40H/42H VDDP RCON0 R13 4.7 k JP44 'strapping' DGND
XPCON[0:5]
HPD[0:7]
R19 AI24 18 R17 AI23 18 R16 AI22 18 R18 AI21 18
C100 47 nF C97 47 nF C98 47 nF C99 47 nF C109 47 nF
P6
AI24
P7
AI23
IPD[0:7]
P9
AI22
P10
AI21
P8
AI2D
R15 AI12 18 R20 AI11 18 R21 56 R22 56 R23 56 R24 56 R25 56 R26 56
C101 47 nF C102 47 nF C110 47 nF AGND
P11
SAA7108AE SAA7109AE
IPCON[0:7]
AI12
P13
AI11
P12
ITRI IGPV IGPH IGP1 IGP0 ICLK IDQ ITRDY AMXCLK ALRCLK ASCLK AMCLK
AI1D
AUDIO[0:3]
R29 AOUT 0
M10
AOUT RTS1 RTS0 RTCO LLC2 LLC RESd CE
RCON[0:2]
VDD(AM8) VDD(AM9) VDD(AN11) VDD(EL9) VDD(EL7) VDD(EG11) VDD(ED10) VDD(ID11) VDD(IF11) VDD(IJ4) VSSAd VSSAd AGND VSSAd VSSAd VSSAd VSSAd VSSEd VSSEd VSSEd VSSEd VSSXd VSSId VSSId VSSId VDD(IJ11) VDD(IL4) VDD(IL11) VDD(XL8) C55 100 nF C53 100 nF C54 100 nF L36 ferrite open AGND DGND C52 100 nF C48 100 nF C51 100 nF C49 100 nF C50 100 nF C60 100 nF C56 100 nF C59 100 nF C57 100 nF C58 100 nF C61 100 nF
BSC[0:2] TDI_D TDO_D TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 XTOUT Y1 24.576 MHz C104 10 pF
JP45 CE_Dec. DGND
XTOUTd XTALOd XTALId
H4 H11 L6 M13
N13 N12 N10 N9 N8 N7 M7
E11 K4 K11
AGND
DGND
DXGND
AGND
DGND
DXGND DGND
P5
0
open 3PAD AGND
MBL790
Fig.53 Application circuit (decoder part).
2004 Jun 29
103
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handbook, full pagewidth +3.3 V digital
Philips Semiconductors
HD-CODEC
+3.3 V analog AGND 1 nF 10 pF 10 pF DGND 0.1 H 27 MHz 0.1 F AGND use one capacitor for each VDDAe and VDDXe VDDAe and VDDXe A10, B6, B9, C9, D9 and D6 D7 D8 C7 VSM HSM_CSYNC GREEN_VBS_CVBS FLTR0 75 75 UY
0.1 F DGND
0.1 F
VDD(DVO) F4
VDDIEe D4
XTALIe A5
XTALOe A6
AGND digital inputs and outputs
AGND FLTR1
AGND
104
SAA7108AE SAA7109AE
C8
RED_CR_C_CVBS 75 75
UC
AGND C6 C5, D5, E4 VSSIe A8 VSSXe B8 VSSAe A9 RSET 1 k A7 DUMP B7 DUMP AGND 12 BLUE_CB_CVBS
AGND FLTR2
AGND
SAA7108AE; SAA7109AE
75
75
UCVBS
AGND
AGND
MBL784
DGND
AGND
AGND
AGND
AGND
Product specification
Fig.54 Application circuit (encoder part).
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, halfpage
C16 120 pF L2 2.7 H C10 390 pF L3 2.7 H C13 560 pF
AGND
JP11 FIN
JP12 FOUT
FILTER 1 = byp. ll act.
MHB912
Fig.55 FLTR0, FLTR1 and FLTR2 as shown in Fig.54.
2004 Jun 29
105
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth
SAA7108AE SAA7109AE
P2 XTALId 32.11 MHz P3 XTALOd P2
SAA7108AE SAA7109AE
P3 XTALOd P2 XTALId 32.11 MHz
SAA7108AE SAA7109AE
P3 XTALOd XTALId 32.11 MHz
4.7 H 1 nF
15 pF
15 pF
33 pF
33 pF
10 pF
10 pF
MBL796
(1a) With 3rd-harmonic quartz. Crystal load = 8 pF.
(1b) With fundamental quartz. Crystal load = 20 pF.
(1c) With fundamental quartz. Crystal load = 8 pF
handbook, full pagewidth
SAA7108AE SAA7109AE
P2 XTALId 24.576 MHz P3 XTALOd P2
SAA7108AE SAA7109AE
P3 XTALOd P2 XTALId 24.576 MHz
SAA7108AE SAA7109AE
P3 XTALOd XTALId 24.576 MHz
4.7 H 1 nF
18 pF
18 pF
39 pF
39 pF
15 pF
15 pF
MBL795
(2a) With 3rd-harmonic quartz. Crystal load = 8 pF.
(2b) With fundamental quartz. Crystal load = 20 pF.
(2c) With fundamental quartz. Crystal load = 8 pF.
SAA7108AE SAA7109AE
P2 XTALId 32.11 MHz or 24.576 MHz n.c. clock P3 XTALOd P2
SAA7108AE SAA7109AE
P3 XTALOd Rs XTALId
MBL794
(3a) With direct clock.
(3b) With fundamental quartz and restricted drive level. When Pdrive of the internal oscillator is too high, a resistance Rs can be placed in series with the oscillator output XTALOd. Note: The decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease.
Fig.56 Oscillator application for decoder part.
2004 Jun 29
106
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth
SAA7108AE SAA7109AE
A5 XTALIe 27.00 MHz A6 XTALOe A5
SAA7108AE SAA7109AE
A6 XTALOe XTALIe 27.00 MHz
4.7 H 1 nF
18 pF
18 pF
39 pF
39 pF
MBL792
(1a) With 3rd-harmonic quartz. Crystal load = 8 pF.
(1b) With fundamental quartz. Crystal load = 20 pF.
handbook, full pagewidth
SAA7108AE SAA7109AE
A5 XTALIe 27.00 MHz n.c. clock A6 XTALOe A5
SAA7108AE SAA7109AE
A6 XTALOe Rs XTALIe
MBL793
(2a) With direct clock.
(2b) With fundamental quartz and restricted drive level. When Pdrive of the internal oscillator is too high, a resistance Rs can be placed in series with the oscillator output XTALOe. Note: The decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease.
Fig.57 Oscillator application for encoder part.
2004 Jun 29
107
Philips Semiconductors
Product specification
HD-CODEC
17.1 Reconstruction filter
SAA7108AE; SAA7109AE
By setting the reference currents of the DACs as shown in Table 49, standard compliant amplitudes can be achieved for all signal combinations; it is assumed that in subaddress 16H, parameter DACF = 0000b, that means the fine adjustment for all DACs in common is set to 0 %. If S-video output is desired, the adjustment for the C (chrominance subcarrier) output should be identical to the one for VBS (luminance plus sync) output.
Figure 55 shows a possible reconstruction filter for the digital-to-analog converters. Due to its cut-off frequency of 6 MHz, it is not suitable for HDTV applications. 17.2 Analog output voltages
The analog output voltages are dependent on the total load (typical value 37.5 ), the digital gain parameters and the I2C-bus settings of the DAC reference currents (analog settings). The digital output signals in front of the DACs under nominal (nominal here stands for the settings given in Tables 75 to 82 for example a standard PAL or NTSC signal) conditions occupy different conversion ranges, as indicated in Table 49 for a 100100 colour bar signal. Table 49 Digital output signals conversion range SET/OUT Digital settings Digital output Analog settings Analog output 17.3
CVBS, SYNC TIP-TO-WHITE VBS, SYNC TIP-TO-WHITE see Tables 75 to 82 1014 e.g. B DAC = 1FH 1.23 V (p-p) see Tables 75 to 82 881 e.g. G DAC = 1BH 1.00 V (p-p)
RGB, BLACK-TO-WHITE see Table 70 876 e.g. R DAC = G DAC = B DAC = 0BH 0.70 V (p-p)
Suggestions for a board layout
Use separate ground planes for analog and digital ground. Connect these planes only at one point directly under the device, by using a 0 resistor directly at the supply stage. Use separate supply lines for the analog and digital supply. Place the supply decoupling capacitors close to the supply pins. Use Lbead (ferrite coil) in each digital supply line close to the decoupling capacitors to minimize radiation energy (EMC). Place the analog coupling (clamp) capacitors close to the analog input pins. Place the analog termination resistors close to the coupling capacitors. Be careful of hidden layout capacitors around the crystal application.
Use serial resistors in clock, sync and data lines, to avoid clock or data reflection effects and to soften data energy. The SAA7108AE; SAA7109AE crystal temperature depends on the PCB it is soldered on. For normal airflow conditions at a maximum ambient temperature of 70 C it will be sufficient to provide: * PCB dimensions at least 2000 mm2 * PCB at least 4 layers * At least 50 vias (connecting PCB layers) close to the chip * Metal coverage at least 60 % on at least 2 PCB layers near the chip.
2004 Jun 29
108
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HD-CODEC
18.1
Digital video encoder part
Table 50 Slave receiver bit allocation map (slave address 88H) REGISTER FUNCTION Status byte (read only) Null Common DAC adjust fine R DAC adjust coarse G DAC adjust coarse B DAC adjust coarse MSM threshold Monitor sense mode Chip ID (02B or 03B, read only) Wide screen signal Wide screen signal Real-time control, burst start Sync reset enable, burst end Copy generation 0 Copy generation 1 CG enable, copy generation 2 Output port control Null Input path control Gain luminance for RGB Gain colour difference for RGB Input port control 1 VPS enable, input control 2 VPS byte 5 VPS byte 11 VPS byte 12 VPS byte 13 VPS byte 14 SUB ADDR. (HEX) 00 01 to 15 16 17 18 19 1A 1B 1C 26 27 28 29 2A 2B 2C 2D 2E to 36 37 38 39 3A 54 55 56 57 58 59 D7 VER2
(1) (1) (1) (1) (1)
D6 VER1
(1) (1) (1) (1) (1)
D5 VER0
(1) (1) (1) (1) (1)
D4 CCRDO
(1) (1)
D3 CCRDE
(1)
D2
(1) (1)
D1 FSEQ
(1)
D0 O_E
(1)
RDACC4 GDACC4 BDACC4 MSMT4
(1)
DACF3 RDACC3 GDACC3 BDACC3 MSMT3
(1)
DACF2 RDACC2 GDACC2 BDACC2 MSMT2 RCOMP CID2 WSS2 WSS10 BS2 BE2 CG02 CG10 CG18 CLK2EN
(1)
DACF1 RDACC1 GDACC1 BDACC1 MSMT1 GCOMP CID1 WSS1 WSS9 BS1 BE1 CG01 CG09 CG17 CVBSEN2
(1)
DACF0 RDACC0 GDACC0 BDACC0 MSMT0 BCOMP CID0 WSS0 WSS8 BS0 BE0 CG00 CG08 CG16
(1) (1)
MSMT7 MSM CID7 WSS7 WSSON
(1)
MSMT6 MSA CID6 WSS6
(1) (1) (1)
SRES CG07 CG15 CGEN VBSEN
(1) (1) (1) (1)
CG06 CG14
(1)
MSMT5 MSOE CID5 WSS5 WSS13 BS5 BE5 CG05 CG13
(1)
CID4 WSS4 WSS12 BS4 BE4 CG04 CG12
(1)
CVBSEN1
(1)
CVBSEN0
(1)
CEN
(1)
CID3 WSS3 WSS11 BS3 BE3 CG03 CG11 CG19 ENCOFF
(1) (1)
SAA7108AE; SAA7109AE
YUPSC
(1) (1) (1) (1)
YFIL1
(1) (1)
CBENB VPSEN VPS57 VPS117 VPS127 VPS137 VPS147
VPS56 VPS116 VPS126 VPS136 VPS146
SYNTV GPVAL VPS55 VPS115 VPS125 VPS135 VPS145
YFIL0 GY4 GCD4 SYMP GPEN VPS54 VPS114 VPS124 VPS134 VPS144
GY3 GCD3 DEMOFF
(1)
CZOOM GY2 GCD2 CSYNC
(1)
VPS53 VPS113 VPS123 VPS133 VPS143
VPS52 VPS112 VPS122 VPS132 VPS142
IGAIN GY1 GCD1 Y2C EDGE VPS51 VPS111 VPS121 VPS131 VPS141
XINT GY0 GCD0 UV2C SLOT VPS50 VPS110 VPS120 VPS130 VPS140
Product specification
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HD-CODEC
REGISTER FUNCTION Chrominance phase Gain U Gain V Gain U MSB, black level Gain V MSB, blanking level CCR, blanking level VBI Null Standard control Burst amplitude Subcarrier 0 Subcarrier 1 Subcarrier 2 Subcarrier 3 Line 21 odd 0 Line 21 odd 1 Line 21 even 0 Line 21 even 1 Null Trigger control Trigger control Multi control Closed Caption, teletext enable Active display window horizontal start Active display window horizontal end MSBs ADWH TTX request horizontal start TTX request horizontal delay CSYNC advance TTX odd request vertical start TTX odd request vertical end
D7 CHPS7 GAINU7 GAINV7 GAINU8 GAINV8 CCRS1
(1)
D6 CHPS6 GAINU6 GAINV6
(1) (1)
D5 CHPS5 GAINU5 GAINV5 BLCKL5 BLNNL5 BLNVB5
(1)
D4 CHPS4 GAINU4 GAINV4 BLCKL4 BLNNL4 BLNVB4
(1)
D3 CHPS3 GAINU3 GAINV3 BLCKL3 BLNNL3 BLNVB3
(1) (1)
D2 CHPS2 GAINU2 GAINV2 BLCKL2 BLNNL2 BLNVB2
(1)
D1 CHPS1 GAINU1 GAINV1 BLCKL1 BLNNL1 BLNVB1
(1)
D0 CHPS0 GAINU0 GAINV0 BLCKL0 BLNNL0 BLNVB0
(1)
CCRS0
(1)
DOWND RTCE FSC07 FSC15 FSC23 FSC31 L21O07 L21O17 L21E07 L21E17
(1)
DOWNA BSTA6 FSC06 FSC14 FSC22 FSC30 L21O06 L21O16 L21E06 L21E16
(1)
INPI BSTA5 FSC05 FSC13 FSC21 FSC29 L21O05 L21O15 L21E05 L21E15
(1)
YGS BSTA4 FSC04 FSC12 FSC20 FSC28 L21O04 L21O14 L21E04 L21E14
(1)
BSTA3 FSC03 FSC11 FSC19 FSC27 L21O03 L21O13 L21E03 L21E13
(1)
SCBW BSTA2 FSC02 FSC10 FSC18 FSC26 L21O02 L21O12 L21E02 L21E12
(1)
PAL BSTA1 FSC01 FSC09 FSC17 FSC25 L21O01 L21O11 L21E01 L21E11
(1)
FISE BSTA0 FSC00 FSC08 FSC16 FSC24 L21O00 L21O10 L21E00 L21E10
(1)
HTRIG7 HTRIG10 NVTRIG CCEN1 ADWHS7 ADWHE7
(1)
HTRIG6 HTRIG9 BLCKON CCEN0 ADWHS6 ADWHE6 ADWHE10 TTXHS6
(1)
HTRIG5 HTRIG8 PHRES1 TTXEN ADWHS5 ADWHE5 ADWHE9 TTXHS5
(1)
HTRIG4 VTRIG4 PHRES0 SCCLN4 ADWHS4 ADWHE4 ADWHE8 TTXHS4
(1)
HTRIG3 VTRIG3 LDEL1 SCCLN3 ADWHS3 ADWHE3
(1)
HTRIG2 VTRIG2 LDEL0 SCCLN2 ADWHS2 ADWHE2 ADWHS10 TTXHS2 TTXHD2
(1)
HTRIG1 VTRIG1 FLC1 SCCLN1 ADWHS1 ADWHE1 ADWHS9 TTXHS1 TTXHD1
(1)
HTRIG0 VTRIG0 FLC0 SCCLN0 ADWHS0 ADWHE0 ADWHS8 TTXHS0 TTXHD0
(1)
SAA7108AE; SAA7109AE
Product specification
TTXHS7
(1)
CSYNCA4 TTXOVS7 TTXOVE7
CSYNCA3 CSYNCA2 CSYNCA1 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVE6 TTXOVE5 TTXOVE4
TTXHS3 TTXHD3 CSYNCA0 TTXOVS3 TTXOVE3
TTXOVS2 TTXOVE2
TTXOVS1 TTXOVE1
TTXOVS0 TTXOVE0
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HD-CODEC
REGISTER FUNCTION TTX even request vertical start TTX even request vertical end First active line Last active line TTX mode, MSB vertical Null Disable TTX line Disable TTX line FIFO status (read only) Pixel clock 0 Pixel clock 1 Pixel clock 2 Pixel clock control FIFO control Null Horizontal offset Pixel number Vertical offset odd Vertical offset even MSBs Line number Scaler CTRL, MCB YPIX Sync control Line length Input delay, MSB line length Horizontal increment Vertical increment MSBs vertical and horizontal increment Weighting factor odd Weighting factor even Weighting factor MSB
D7 TTXEVS7 TTXEVE7 FAL7 LAL7 TTX60
(1)
D6 TTXEVS6 TTXEVE6 FAL6 LAL6 LAL8
(1)
D5 TTXEVS5 TTXEVE5 FAL5 LAL5 TTXO
(1)
D4 TTXEVS4 TTXEVE4 FAL4 LAL4 FAL8
(1)
D3 TTXEVS3 TTXEVE3 FAL3 LAL3 TTXEVE8
(1)
D2 TTXEVS2 TTXEVE2 FAL2 LAL2 TTXOVE8
(1)
D1 TTXEVS1 TTXEVE1 FAL1 LAL1 TTXEVS8
(1)
D0 TTXEVS0 TTXEVE0 FAL0 LAL0 TTXOVS8
(1)
LINE12 LINE20
(1)
LINE11 LINE19
(1)
LINE10 LINE18
(1)
LINE9 LINE17
(1)
LINE8 LINE16 IFERR PCL03 PCL11 PCL19 PCLE1 FILI3
(1)
LINE7 LINE15 BFERR PCL02 PCL10 PCL18 PCLE0 FILI2
(1)
LINE6 LINE14 OVFL PCL01 PCL09 PCL17 PCLI1 FILI1
(1)
LINE5 LINE13 UDFL PCL00 PCL08 PCL16 PCLI0 FILI0
(1)
PCL07 PCL15 PCL23 DCLK EIDIV
(1)
PCL06 PCL14 PCL22 PCLSY
(1) (1)
PCL05 PCL13 PCL21 IFRA
(1) (1)
PCL04 PCL12 PCL20 IFBP
(1) (1)
XOFS7 XPIX7 YOFSO7 YOFSE7 YOFSE9 YPIX7 EFS HFS HLEN7 IDEL3 XINC7 YINC7 YINC11
XOFS6 XPIX6 YOFSO6 YOFSE6 YOFSE8 YPIX6 PCBN VFS HLEN6 IDEL2 XINC6 YINC6 YINC10
XOFS5 XPIX5 YOFSO5 YOFSE5 YOFSO9 YPIX5 SLAVE OFS HLEN5 IDEL1 XINC5 YINC5 YINC9
XOFS4 XPIX4 YOFSO4 YOFSE4 YOFSO8 YPIX4 ILC PFS HLEN4 IDEL0 XINC4 YINC4 YINC8
XOFS3 XPIX3 YOFSO3 YOFSE3 XPIX9 YPIX3 YFIL OVS HLEN3 HLEN11 XINC3 YINC3 XINC11
XOFS2 XPIX2 YOFSO2 YOFSE2 XPIX8 YPIX2
(1)
PVS HLEN2 HLEN10 XINC2 YINC2 XINC10
XOFS1 XPIX1 YOFSO1 YOFSE1 XOFS9 YPIX1 YPIX9 OHS HLEN1 HLEN9 XINC1 YINC1 XINC9
XOFS0 XPIX0 YOFSO0 YOFSE0 XOFS8 YPIX0 YPIX8 PHS HLEN0 HLEN8 XINC0 YINC0 XINC8 YIWGTO0 YIWGTE0 YIWGTO8
SAA7108AE; SAA7109AE
Product specification
YIWGTO7 YIWGTO6 YIWGTO5 YIWGTE7 YIWGTE6 YIWGTE5 YIWGTE11 YIWGTE10 YIWGTE9
YIWGTO4 YIWGTO3 YIWGTO2 YIWGTO1 YIWGTE4 YIWGTE3 YIWGTE2 YIWGTE1 YIWGTE8 YIWGTO11 YIWGTO10 YIWGTO9
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HD-CODEC
REGISTER FUNCTION Vertical line skip Blank enable for NI-bypass, vertical line skip MSB Border colour Y Border colour U Border colour V HD sync line count array HD sync line type array HD sync line pattern array HD sync value array HD sync trigger state 1 HD sync trigger state 2 HD sync trigger state 3 HD sync trigger state 4 HD sync trigger phase x HD sync trigger phase y HD output control Cursor colour 1 R Cursor colour 1 G Cursor colour 1 B Cursor colour 2 R Cursor colour 2 G Cursor colour 2 B Auxiliary cursor colour R Auxiliary cursor colour G Auxiliary cursor colour B Horizontal cursor position Horizontal hot spot, MSB XCP Vertical cursor position Vertical hot spot, MSB YCP
D7 YSKIP7 BLEN BCY7 BCU7 BCV7
D6 YSKIP6
(1)
D5 YSKIP5
(1)
D4 YSKIP4
(1)
D3 YSKIP3 YSKIP11
D2 YSKIP2 YSKIP10
D1 YSKIP1 YSKIP9 BCY1 BCU1 BCV1
D0 YSKIP0 YSKIP8 BCY0 BCU0 BCV0
BCY6 BCU6 BCV6
HLCT7 HLCPT3 HDCT7
(1)
HTX7
(1)
HLCT6 HLCPT2 HDCT6 HEPT2 HTX6
(1)
HTY7
(1) (1)
HTY6
(1) (1)
BCY4 BCY3 BCY2 BCU4 BCU3 BCU2 BCV4 BCV3 BCV2 RAM address (see Table 123) RAM address (see Table 125) RAM address (see Table 127) RAM address (see Table 129) HLCT5 HLCT4 HLCT3 HLCT2 HLCPT1 HLCPT0 HLPPT1 HLPPT0 HDCT5 HDCT4 HDCT3 HDCT2 (1) (1) HEPT1 HEPT0 HTX5 HTX4 HTX3 HTX2 (1) (1) HTX11 HTX10 HTY5 HTY4 HTY3 HTY2
(1) (1) (1) (1) (1) (1)
BCY5 BCU5 BCV5
CC1R7 CC1G7 CC1B7 CC2R7 CC2G7 CC2B7 AUXR7 AUXG7 AUXB7 XCP7 XHS4 YCP7 YHS4
CC1R6 CC1G6 CC1B6 CC2R6 CC2G6 CC2B6 AUXR6 AUXG6 AUXB6 XCP6 XHS3 YCP6 YHS3
CC1R5 CC1G5 CC1B5 CC2R5 CC2G5 CC2B5 AUXR5 AUXG5 AUXB5 XCP5 XHS2 YCP5 YHS2
CC1R4 CC1G4 CC1B4 CC2R4 CC2G4 CC2B4 AUXR4 AUXG4 AUXB4 XCP4 XHS1 YCP4 YHS1
HDSYE CC1R3 CC1G3 CC1B3 CC2R3 CC2G3 CC2B3 AUXR3 AUXG3 AUXB3 XCP3 XHS0 YCP3 YHS0
HDTC CC1R2 CC1G2 CC1B2 CC2R2 CC2G2 CC2B2 AUXR2 AUXG2 AUXB2 XCP2 XCP10 YCP2
(1)
HLCT1 HLCT9 HDCT1 HDCT9 HTX1 HTX9 HTY1 HTY9 HDGY CC1R1 CC1G1 CC1B1 CC2R1 CC2G1 CC2B1 AUXR1 AUXG1 AUXB1 XCP1 XCP9 YCP1 YCP9
HLCT0 HLCT8 HDCT0 HDCT8 HTX0 HTX8 HTY0 HTY8 HDIP CC1R0 CC1G0 CC1B0 CC2R0 CC2G0 CC2B0 AUXR0 AUXG0 AUXB0 XCP0 XCP8 YCP0 YCP8
SAA7108AE; SAA7109AE
Product specification
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HD-CODEC
REGISTER FUNCTION Input path control Cursor bit map Colour look-up table Note
D7 LUTOFF
D6 CMODE
D5 LUTL
D4 IF2
D3 IF1
D2 IF0
D1 MATOFF
D0 DFOFF
RAM address (see Table 144) RAM address (see Table 145)
1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
SAA7108AE; SAA7109AE
Product specification
Philips Semiconductors
Product specification
HD-CODEC
18.1.1 I2C-BUS FORMAT
SAA7108AE; SAA7109AE
Table 51 I2C-bus write access to control registers; see Table 57 S 10001000 A SUBADDRESS A DATA 0 A -------DATA n A P
Table 52 I2C-bus write access to the HD line count array (subaddress D0H); see Table 57 S 1 0 0 0 1 0 0 0 A D0H A RAM ADDRESS A DATA 00 A DATA 01 A -------DATA n A P
Table 53 I2C-bus write access to cursor bit map (subaddress FEH); see Table 57 S 1 0 0 0 1 0 0 0 A FEH A RAM ADDRESS A DATA 0 A -------DATA n A P
Table 54 I2C-bus write access to colour look-up table (subaddress FFH); see Table 57 S 10001000 A FFH A RAM ADDRESS A DATA 0R A DATA 0G A DATA 0B A -------P
Table 55 I2C-bus read access to control registers; see Table 57 S 10001000 A SUBADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Am P
Table 56 I2C-bus read access to cursor bit map or colour LUT; see Table 57 S 1 0 0 0 1 0 0 0 A FEH A RAM ADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Am P or FFH Table 57 Explanations of Tables 51 to 56 CODE S Sr 1 0 0 0 1 0 0 X; note 1 A Am SUBADDRESS; note 2 DATA -------P RAM ADDRESS Notes 1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read. 2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed. START condition repeated START condition slave address acknowledge generated by the slave acknowledge generated by the master subaddress byte data byte continued data bytes and acknowledges STOP condition start address for RAM access DESCRIPTION
2004 Jun 29
114
Philips Semiconductors
Product specification
HD-CODEC
18.1.2 SLAVE RECEIVER
SAA7108AE; SAA7109AE
Table 58 Subaddress 16H DATA BYTE DACF DESCRIPTION output level adjustment fine in 1 % steps for all DACs; default after reset is 00H; see Table 59
Table 59 Fine adjustment of DAC output voltage BINARY 0111 0110 0101 0100 0011 0010 0001 0000 1000 1001 1010 1011 1100 1101 1110 1111 Table 60 Subaddresses 17H to 19H DATA BYTE RDACC GDACC BDACC DESCRIPTION output level coarse adjustment for RED DAC; default after reset is 1BH for output of C signal 00000b 0.585 V to 11111b 1.240 V at 37.5 nominal for full-scale conversion output level coarse adjustment for GREEN DAC; default after reset is 1BH for output of VBS signal 00000b 0.585 V to 11111b 1.240 V at 37.5 nominal for full-scale conversion output level coarse adjustment for BLUE DAC; default after reset is 1FH for output of CVBS signal 00000b 0.585 V to 11111b 1.240 V at 37.5 nominal for full-scale conversion GAIN (%) 7 6 5 4 3 2 1 0 0 -1 -2 -3 -4 -5 -6 -7
Table 61 Subaddress 1AH DATA BYTE MSMT DESCRIPTION monitor sense mode threshold for DAC output voltage, should be set to 70
2004 Jun 29
115
Philips Semiconductors
Product specification
HD-CODEC
Table 62 Subaddress 1BH DATA BYTE MSM MSA LOGIC LEVEL 0 1 0 1 MSOE RCOMP (read only) GCOMP (read only) BCOMP (read only) 0 1 0 1 0 1 0 1 monitor sense mode on
SAA7108AE; SAA7109AE
DESCRIPTION monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset automatic monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset automatic monitor sense mode on if MSM = 0 pin TVD is active pin TVD is 3-state; default after reset check comparator at DAC on pin RED_CR_C_CVBS is active, output is loaded check comparator at DAC on pin RED_CR_C_CVBS is inactive, output is not loaded check comparator at DAC on pin GREEN_VBS_CVBS is active, output is loaded check comparator at DAC on pin GREEN_VBS_CVBS is inactive, output is not loaded check comparator at DAC on pin BLUE_CB_CVBS is active, output is loaded check comparator at DAC on pin BLUE_CB_CVBS is inactive, output is not loaded
Table 63 Subaddresses 26H and 27H DATA BYTE WSS LOGIC LEVEL - wide screen signalling bits 3 to 0 = aspect ratio 7 to 4 = enhanced services 10 to 8 = subtitles 13 to 11 = reserved WSSON 0 1 wide screen signalling output is disabled; default after reset wide screen signalling output is enabled DESCRIPTION
Table 64 Subaddress 28H DATA BYTE BS LOGIC LEVEL - DESCRIPTION starting point of burst in clock cycles REMARKS PAL: BS = 33 (21H); default after reset if strapping pin FSVGC tied to HIGH NTSC: BS = 25 (19H); default after reset if strapping pin FSVGC tied to LOW
2004 Jun 29
116
Philips Semiconductors
Product specification
HD-CODEC
Table 65 Subaddress 29H DATA BYTE SRES LOGIC LEVEL 0 1 BE - DESCRIPTION pin TTX_SRES accepts a teletext bit stream (TTX) pin TTX_SRES accepts a sync reset input (SRES) ending point of burst in clock cycles
SAA7108AE; SAA7109AE
REMARKS default after reset a HIGH impulse resets synchronization of the encoder (first field, first line) PAL: BE = 29 (1DH); default after reset if strapping pin FSVGC tied to HIGH NTSC: BE = 29 (1DH); default after reset if strapping pin FSVGC tied to LOW
Table 66 Subaddresses 2AH to 2CH DATA BYTE CG LOGIC LEVEL - DESCRIPTION LSB of the respective bytes are encoded immediately after run-in, the MSBs of the respective bytes have to carry the CRCC bits, in accordance with the definition of copy generation management system encoding format. copy generation data output is disabled; default after reset copy generation data output is enabled
CGEN
0 1
Table 67 Subaddress 2DH DATA BYTE VBSEN LOGIC LEVEL 0 1 CVBSEN1 0 1 CVBSEN0 CEN 0 1 0 1 ENCOFF CLK2EN 0 1 0 1 CVBSEN2 0 1 DESCRIPTION pin GREEN_VBS_CVBS provides a component GREEN signal (CVBSEN1 = 0) or CVBS signal (CVBSEN1 = 1) pin GREEN_VBS_CVBS provides a luminance (VBS) signal; default after reset pin GREEN_VBS_CVBS provides a component GREEN (G) or luminance (VBS) signal; default after reset pin GREEN_VBS_CVBS provides a CVBS signal pin BLUE_CB_CVBS provides a component BLUE (B) or colour difference BLUE (CB) signal pin BLUE_CB_CVBS provides a CVBS signal; default after reset pin RED_CR_C_CVBS provides a component RED (R) or colour difference RED (CR) signal pin RED_CR_C_CVBS provides a chrominance signal (C) as modulated subcarrier for S-video; default after reset encoder is active; default after reset encoder bypass, DACs are provided with RGB signal after cursor insertion block pin TTXRQ_XCLKO2 provides a teletext request signal (TTXRQ) pin TTXRQ_XCLKO2 provides the buffered crystal clock divided by two (13.5 MHz); default after reset pin RED_CR_C_CVBS provides a signal according to CEN; default after reset pin RED_CR_C_CVBS provides a CVBS signal
2004 Jun 29
117
Philips Semiconductors
Product specification
HD-CODEC
Table 68 Subaddress 37H DATA BYTE YUPSC YFIL CZOOM IGAIN XINT LOGIC LEVEL 0 1 - 0 1 0 1 0 1 vertical upscaling is enabled
SAA7108AE; SAA7109AE
DESCRIPTION normal operation of the vertical scaler; default after reset controls the vertical interpolation filter, see Table 69; the filter is not available if YUPSC = 1 normal operation of the cursor generator; default after reset the cursor will be zoomed by a factor of 2 in both directions expected input level swing is 16 to 235 (8-bit RGB); default after reset expected input level swing is 0 to 255 (8-bit RGB) no horizontal interpolation filter; default after reset interpolation filter for horizontal upscaling is active
Table 69 Logic levels and function of YFIL DATA BYTE DESCRIPTION YFIL1 0 0 1 1 YFIL0 0 1 0 1 no filter active; default after reset filter is inserted before vertical scaling filter is inserted after vertical scaling; YSKIP should be logic 0 reserved
Table 70 Subaddresses 38H and 39H DATA BYTE GY4 to GY0 GCD4 to GCD0 DESCRIPTION Gain luminance of RGB (CR, Y and CB) output, ranging from (1 - 1632) to (1 + 1532). Suggested nominal value = 0, depending on external application. Gain colour difference of RGB (CR, Y and CB) output, ranging from (1 - 1632) to (1 + 1532). Suggested nominal value = 0, depending on external application.
Table 71 Subaddress 3AH DATA BYTE CBENB SYNTV LOGIC LEVEL 0 1 0 1 SYMP 0 1 data from input ports is encoded colour bar with fixed colours is encoded in slave mode, the encoder is only synchronized at the beginning of an odd field; default after reset in slave mode, the encoder receives a vertical sync signal horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default after reset horizontal and vertical trigger is decoded out of "ITU-R BT.656" compatible data at PD port DESCRIPTION
2004 Jun 29
118
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
DATA BYTE DEMOFF CSYNC
LOGIC LEVEL 0 1 0 1
DESCRIPTION Y-CB-CR to RGB dematrix is active; default after reset Y-CB-CR to RGB dematrix is bypassed pin HSM_CSYNC provides a horizontal sync for non-interlaced VGA components output (at PIXCLK) pin HSM_CSYNC provides a composite sync for interlaced components output (at XTAL clock) input luminance data is twos complement from PD input port input luminance data is straight binary from PD input port; default after reset input colour difference data is twos complement from PD input port input colour difference data is straight binary from PD input port; default after reset
Y2C UV2C
0 1 0 1
Table 72 Subaddress 54H DATA BYTE VPSEN GPVAL GPEN EDGE LOGIC LEVEL 0 1 0 1 0 1 0 1 SLOT 0 1 DESCRIPTION video programming system data insertion is disabled; default after reset video programming system data insertion in line 16 is enabled pin VSM provides a LOW level if GPEN = 1 pin VSM provides a HIGH level if GPEN = 1 pin VSM provides a vertical sync for a monitor; default after reset pin VSM provides a constant signal according to GPVAL input data is sampled with inverse clock edges input data is sampled with the clock edges specified in Tables 9 to 14; default after reset normal assignment of the input data to the clock edge; default after reset correct time misalignment due to inverted assignment of input data to the clock edge
Table 73 Subaddresses 55H to 59H DATA BYTE VPS5 VPS11 VPS12 VPS13 VPS14 DESCRIPTION fifth byte of video programming system data eleventh byte of video programming system data twelfth byte of video programming system data thirteenth byte of video programming system data fourteenth byte of video programming system data REMARKS in line 16; LSB first; all other bytes are not relevant for VPS
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119
Philips Semiconductors
Product specification
HD-CODEC
Table 74 Subaddress 5AH; note 1 DATA BYTE CHPS DESCRIPTION phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees VALUE 6BH 16H 25H 46H Note 1. The default value after reset is 00H. Table 75 Subaddresses 5BH and 5DH DATA BYTE GAINU DESCRIPTION variable gain for CB signal; input representation in accordance with "ITU-R BT.601" CONDITIONS white-to-black = 92.5 IRE GAINU = 0 GAINU = 118 (76H) white-to-black = 100 IRE GAINU = 0 GAINU = 125 (7DH) Table 76 Subaddresses 5CH and 5EH DATA BYTE GAINV DESCRIPTION variable gain for CR signal; input representation in accordance with "ITU-R BT.601" CONDITIONS white-to-black = 92.5 IRE GAINV = 0 GAINV = 165 (A5H) white-to-black = 100 IRE GAINV = 0 GAINV = 175 (AFH) Table 77 Subaddress 5DH DATA BYTE BLCKL DESCRIPTION variable black level; input representation in accordance with "ITU-R BT.601" CONDITIONS white-to-sync = 140 IRE; note 1 BLCKL = 0; note 1 white-to-sync = 143 IRE; note 2 BLCKL = 0; note 2
SAA7108AE; SAA7109AE
RESULT PAL B/G and data from input ports in master mode PAL B/G and data from look-up table NTSC M and data from input ports in master mode NTSC M and data from look-up table
REMARKS GAINU = -2.17 x nominal to +2.16 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal GAINU = -2.05 x nominal to +2.04 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal
REMARKS GAINV = -1.55 x nominal to +1.55 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal GAINV = -1.46 x nominal to +1.46 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal
REMARKS recommended value: BLCKL = 58 (3AH) output black level = 29 IRE recommended value: BLCKL = 51 (33H) output black level = 27 IRE
BLCKL = 63 (3FH); note 1 output black level = 49 IRE
BLCKL = 63 (3FH); note 2 output black level = 47 IRE Notes 1. Output black level/IRE = BLCKL x 2/6.29 + 28.9. 2. Output black level/IRE = BLCKL x 2/6.18 + 26.5.
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120
Philips Semiconductors
Product specification
HD-CODEC
Table 78 Subaddress 5EH DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS white-to-sync = 140 IRE; note 1 BLNNL = 0; note 1 BLNNL = 63 (3FH); note 1 white-to-sync = 143 IRE; note 2 BLNNL = 0; note 2 BLNNL = 63 (3FH); note 2 Notes 1. Output black level/IRE = BLNNL x 2/6.29 + 25.4.
SAA7108AE; SAA7109AE
REMARKS recommended value: BLNNL = 46 (2EH) output blanking level = 25 IRE output blanking level = 45 IRE recommended value: BLNNL = 53 (35H) output blanking level = 26 IRE output blanking level = 46 IRE
2. Output black level/IRE = BLNNL x 2/6.18 + 25.9; default after reset: 35H. Table 79 Subaddress 5FH DATA BYTE CCRS BLNVB DESCRIPTION select cross-colour reduction filter in luminance; see Table 80 variable blanking level during vertical blanking interval is typically identical to value of BLNNL
Table 80 Logic levels and function of CCRS CCRS1 0 0 1 1 CCRS0 0 1 0 1 DESCRIPTION no cross-colour reduction; for overall transfer characteristic of luminance see Fig.7 cross-colour reduction #1 active; for overall transfer characteristic see Fig.7 cross-colour reduction #2 active; for overall transfer characteristic see Fig.7 cross-colour reduction #3 active; for overall transfer characteristic see Fig.7
Table 81 Subaddress 61H DATA BYTE DOWND DOWNA INPI YGS SCBW LOGIC LEVEL 0 1 0 1 0 1 0 1 0 1 DESCRIPTION digital core in normal operational mode; default after reset digital core in sleep mode and is reactivated with an I2C-bus address DACs in normal operational mode; default after reset DACs in Power-down mode PAL switch phase is nominal; default after reset PAL switch is inverted compared to nominal if RTCE = 1 luminance gain for white - black 100 IRE luminance gain for white - black 92.5 IRE including 7.5 IRE set-up of black enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 5 and 6) standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 5 and 6); default after reset
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121
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
DATA BYTE PAL FISE
LOGIC LEVEL 0 1 0 1
DESCRIPTION NTSC encoding (non-alternating V component) PAL encoding (alternating V component) 864 total pixel clocks per line 858 total pixel clocks per line
Table 82 Subaddress 62H DATA BYTE RTCE LOGIC LEVEL 0 1 DESCRIPTION CONDITIONS REMARKS
no real-time control of generated subcarrier frequency; default after reset real-time control of generated subcarrier frequency through a Philips video decoder; for a specification of the RTC protocol see document "RTC Functional Description", available on request recommended value: amplitude of colour burst; input white-to-black = 92.5 IRE; representation in accordance burst = 40 IRE; NTSC encoding BSTA = 63 (3FH) with "ITU-R BT.601" BSTA = 0 to 2.02 x nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 2.82 x nominal white-to-black = 100 IRE; recommended value: burst = 43 IRE; NTSC encoding BSTA = 67 (43H) BSTA = 0 to 1.90 x nominal white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 x nominal recommended value: BSTA = 47 (2FH); default after reset recommended value: BSTA = 45 (2DH)
BSTA
-
Table 83 Subaddresses 63H to 66H (four bytes to program subcarrier frequency) DATA BYTE FSC0 to FSC3 DESCRIPTION ffsc = subcarrier frequency (in multiples of line frequency); fllc = clock frequency (in multiples of line frequency) CONDITIONS f fsc 32 FSC = round ------- x 2 ; f llc note 1 REMARKS FSC3 = most significant byte; FSC0 = least significant byte
Note 1. Examples: a) NTSC M: ffsc = 227.5, fllc = 1716 FSC = 569408543 (21F07C1FH). b) PAL B/G: ffsc = 283.7516, fllc = 1728 FSC = 705268427 (2A098ACBH). Table 84 Subaddresses 67H to 6AH DATA BYTE L21O0 L21O1 L21E0 L21E1 2004 Jun 29 DESCRIPTION first byte of captioning data, odd field REMARKS
LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes second byte of captioning data, odd field have to carry the parity bit, in accordance with the definition first byte of extended data, even field of line 21 encoding format. second byte of extended data, even field 122
Philips Semiconductors
Product specification
HD-CODEC
Table 85 Subaddresses 6CH and 6DH DATA BYTE HTRIG DESCRIPTION
SAA7108AE; SAA7109AE
sets the horizontal trigger phase related to chip-internal horizontal input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of all internally generated timing signals; the default value is 0
Table 86 Subaddress 6DH DATA BYTE VTRIG DESCRIPTION sets the vertical trigger phase related to chip-internal vertical input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; variation range of VTRIG = 0 to 31 (1FH); the default value is 0 Table 87 Subaddress 6EH DATA BYTE NVTRIG BLCKON PHRES LDEL FLC LOGIC LEVEL 0 1 0 1 - - - DESCRIPTION values of the VTRIG register are positive values of the VTRIG register are negative encoder in normal operation mode; default after reset output signal is forced to blanking level selects the phase reset mode of the colour subcarrier generator; see Table 88 selects the delay on luminance path with reference to chrominance path; see Table 89 field length control; see Table 90
Table 88 Logic levels and function of PHRES DATA BYTE DESCRIPTION PHRES1 0 0 1 1 PHRES0 0 1 0 1 no subcarrier reset subcarrier reset every two lines subcarrier reset every eight fields subcarrier reset every four fields
Table 89 Logic levels and function of LDEL DATA BYTE DESCRIPTION LDEL1 0 0 1 1 LDEL0 0 1 0 1 no luminance delay; default after reset 1 LLC luminance delay 2 LLC luminance delay 3 LLC luminance delay
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123
Philips Semiconductors
Product specification
HD-CODEC
Table 90 Logic levels and function of FLC DATA BYTE
SAA7108AE; SAA7109AE
DESCRIPTION FLC1 0 0 1 1 FLC0 0 1 0 1 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 91 Subaddress 6FH DATA BYTE CCEN TTXEN SCCLN LOGIC LEVEL - 0 1 - DESCRIPTION enables individual line 21 encoding; see Table 92 disables teletext insertion; default after reset enables teletext insertion selects the actual line, where Closed Caption or extended data are encoded; line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems
Table 92 Logic levels and function of CCEN DATA BYTE DESCRIPTION CCEN1 0 0 1 1 CCEN0 0 1 0 1 line 21 encoding off; default after reset enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields
Table 93 Subaddresses 70H to 72H DATA BYTE ADWHS DESCRIPTION active display window horizontal start; defines the start of the active TV display portion after the border colour values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed ADWHE active display window horizontal end; defines the end of the active TV display portion before the border colour values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed Table 94 Subaddress 73H DATA BYTE TTXHS DESCRIPTION start of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0); see Fig.51 REMARKS TTXHS = 42H; is default after reset if strapped to PAL TTXHS = 54H; is default after reset if strapped to NTSC
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124
Philips Semiconductors
Product specification
HD-CODEC
Table 95 Subaddress 74H DATA BYTE TTXHD DESCRIPTION
SAA7108AE; SAA7109AE
REMARKS
indicates the delay in clock cycles between rising edge of TTXRQ minimum value: TTXHD = 2; output signal on pin TTXRQ_XCLKO2 (CLK2EN = 0) and valid data at is default after reset pin TTX_SRES
Table 96 Subaddress 75H DATA BYTE CSYNCA DESCRIPTION advanced composite sync against RGB output from 0 XTAL clocks to 31 XTAL clocks
Table 97 Subaddresses 76H, 77H and 7CH DATA BYTE TTXOVS DESCRIPTION first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field line = (TTXOVS + 4) for M-systems line = (TTXOVS + 1) for other systems TTXOVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field line = (TTXOVE + 3) for M-systems line = TTXOVE for other systems Table 98 Subaddresses 78H, 79H and 7CH DATA BYTE TTXEVS DESCRIPTION first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field line = (TTXEVS + 4) for M-systems line = (TTXEVS + 1) for other systems TTXEVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field line = (TTXEVE + 3) for M-systems line = TTXEVE for other systems Table 99 Subaddresses 7AH to 7CH DATA BYTE FAL LAL DESCRIPTION first active line = FAL + 4 for M-systems and FAL + 1 for other systems, measured in lines FAL = 0 coincides with the first field synchronization pulse last active line = LAL + 3 for M-systems and LAL for other system, measured in lines LAL = 0 coincides with the first field synchronization pulse REMARKS TTXEVS = 04H; is default after reset if strapped to PAL TTXEVS = 05H; is default after reset if strapped to NTSC TTXEVE = 16H; is default after reset if strapped to PAL TTXEVE = 10H; is default after reset if strapped to NTSC REMARKS TTXOVS = 05H; is default after reset if strapped to PAL TTXOVS = 06H; is default after reset if strapped to NTSC TTXOVE = 16H; is default after reset if strapped to PAL TTXOVE = 10H; is default after reset if strapped to NTSC
2004 Jun 29
125
Philips Semiconductors
Product specification
HD-CODEC
Table 100 Subaddress 7CH DATA BYTE TTX60 TTXO LOGIC LEVEL 0 1 0 1
SAA7108AE; SAA7109AE
DESCRIPTION enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset enables world standard teletext 60 Hz (FISE = 1) new teletext protocol selected; at each rising edge of TTXRQ a single teletext bit is requested (see Fig.51); default after reset old teletext protocol selected; the encoder provides a window of TTXRQ going HIGH; the length of the window depends on the chosen teletext standard (see Fig.51)
Table 101 Subaddresses 7EH and 7FH DATA BYTE LINE DESCRIPTION individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits, disabled line = LINExx (50 Hz field rate) this bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE Table 102 Subaddresses 81H to 83H DATA BYTE PCL DESCRIPTION defines the frequency of the synthesized pixel clock PIXCLKO; PCL f PIXCLK = ---------- x f XTAL x 8 ; fXTAL = 27 MHz nominal, e.g. 640 x 480 to NTSC M: PCL = 20F63BH; 24 2 640 x 480 to PAL B/G: PCL = 1B5A73H (as by strapping pins)
Table 103 Subaddress 84H DATA BYTE DCLK LOGIC LEVEL 0 1 PCLSY IFRA IFBP PCLE PCLI 0 1 0 1 0 1 - - DESCRIPTION pixel clock input is differential, pin PIXCLKI receives the inverted clock; default after reset pixel clock input is single ended, pin PIXCLKI has no function pixel clock generator runs free; default after reset pixel clock generator gets synchronized with the vertical sync input FIFO gets reset explicitly at falling edge input FIFO gets reset every field; default after reset input FIFO is active input FIFO is bypassed; default after reset controls the divider for the external pixel clock; see Table 104 controls the divider for the internal pixel clock; see Table 105
2004 Jun 29
126
Philips Semiconductors
Product specification
HD-CODEC
Table 104 Logic levels and function of PCLE DATA BYTE
SAA7108AE; SAA7109AE
DESCRIPTION PCLE1 0 0 1 1 PCLE0 0 1 0 1 divider ratio for PIXCLK output is 1 divider ratio for PIXCLK output is 2; default after reset divider ratio for PIXCLK output is 4 divider ratio for PIXCLK output is 8
Table 105 Logic levels and function of PCLI DATA BYTE DESCRIPTION PCLI1 0 0 1 1 PCLI0 0 1 0 1 divider ratio for internal PIXCLK is 1 divider ratio for internal PIXCLK is 2; default after reset divider ratio for internal PIXCLK is 4 not allowed
Table 106 Subaddress 85H DATA BYTE EIDIV FILI LOGIC LEVEL 0 1 - DESCRIPTION input dividers are off; inputs are high-impedance; default after reset input dividers are on; inputs have lower impedance threshold for FIFO internal transfers; nominal value is 8; default after reset
Table 107 Subaddresses 90H and 94H DATA BYTE XOFS DESCRIPTION horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite blanking (CBO) output
Table 108 Subaddresses 91H and 94H DATA BYTE XPIX DESCRIPTION pixel in X direction; defines half the number of active pixels per input line (identical to the length of CBO pulses)
Table 109 Subaddresses 92H and 94H DATA BYTE YOFSO DESCRIPTION vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually, YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing
2004 Jun 29
127
Philips Semiconductors
Product specification
HD-CODEC
Table 110 Subaddresses 93H and 94H DATA BYTE YOFSE DESCRIPTION
SAA7108AE; SAA7109AE
vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually, YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing
Table 111 Subaddresses 95H and 96H DATA BYTE YPIX DESCRIPTION defines the number of requested input lines from the feeding device; number of requested lines = YPIX + YOFSE - YOFSO
Table 112 Subaddress 96H DATA BYTE EFS PCBN SLAVE ILC YFIL LOGIC LEVEL 0 1 0 1 0 1 0 1 0 1 Table 113 Subaddress 97H DATA BYTE HFS LOGIC LEVEL 0 1 VFS 0 1 OFS PFS 0 1 0 1 OVS 0 1 DESCRIPTION horizontal sync is directly derived from input signal (slave mode) at pin HSVGC horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if EFS is set HIGH) vertical sync (field sync) is directly derived from input signal (slave mode) at pin VSVGC vertical sync (field sync) is derived from a frame sync signal (slave mode) at pin FSVGC (only if EFS is set HIGH) pin FSVGC is switched to input pin FSVGC is switched to active output polarity of signal at pin FSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode polarity of signal at pin FSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode pin VSVGC is switched to input pin VSVGC is switched to active output DESCRIPTION frame sync signal at pin FSVGC ignored in slave mode frame sync signal at pin FSVGC accepted in slave mode normal polarity of CBO signal (HIGH during active video) inverted polarity of CBO signal (LOW during active video) the SAA7108AE; SAA7109AE is timing master to the graphics controller the SAA7108AE; SAA7109AE is timing slave to the graphics controller if hardware cursor insertion is active, set LOW for non-interlaced input signals if hardware cursor insertion is active, set HIGH for interlaced input signals luminance sharpness booster disabled luminance sharpness booster enabled
2004 Jun 29
128
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
DATA BYTE PVS
LOGIC LEVEL 0 1
DESCRIPTION polarity of signal at pin VSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode polarity of signal at pin VSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode pin HSVGC is switched to input pin HSVGC is switched to active output polarity of signal at pin HSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode polarity of signal at pin HSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode
OHS PHS
0 1 0 1
Table 114 Subaddresses 98H and 99H DATA BYTE HLEN DESCRIPTION number of PIXCLKs horizontal length; HLEN = ---------------------------------------------------- - 1 line
Table 115 Subaddress 99H DATA BYTE IDEL DESCRIPTION input delay; defines the distance in PIXCLKs between the active edge of CBO and the first received valid pixel
Table 116 Subaddresses 9AH and 9CH DATA BYTE XINC DESCRIPTION number of output pixels ------------------------------------------------------------line incremental fraction of the horizontal scaling engine; XINC = ------------------------------------------------------------- x 4096 number of input pixels --------------------------------------------------------line
Table 117 Subaddresses 9BH and 9CH DATA BYTE YINC DESCRIPTION number of active output lines incremental fraction of the vertical scaling engine; YINC = --------------------------------------------------------------------------- x 4096 number of active input lines
Table 118 Subaddresses 9DH and 9FH DATA BYTE YIWGTO DESCRIPTION YINC weighting factor for the first line of the odd field; YIWGTO = ------------- + 2048 2
2004 Jun 29
129
Philips Semiconductors
Product specification
HD-CODEC
Table 119 Subaddresses 9EH and 9FH DATA BYTE YIWGTE DESCRIPTION
SAA7108AE; SAA7109AE
YINC - YSKIP weighting factor for the first line of the even field; YIWGTE = ------------------------------------2
Table 120 Subaddresses A0H and A1H DATA BYTE YSKIP DESCRIPTION vertical line skip; defines the effectiveness of the anti-flicker filter; YSKIP = 0: most effective; YSKIP = 4095: anti-flicker filter switched off
Table 121 Subaddress A1H DATA BYTE BLEN LOGIC LEVEL 0 1 DESCRIPTION no internal blanking for non-interlaced graphics in bypass mode; default after reset forced internal blanking for non-interlaced graphics in bypass mode
Table 122 Subaddresses A2H to A4H DATA BYTE BCY, BCU and BCV DESCRIPTION luminance and colour difference portion of border colour in underscan area
Table 123 Subaddress D0H DATA BYTE HLCA DESCRIPTION RAM start address for the HD sync line count array; the byte following subaddress D0 points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. Each line count array entry consists of 2 bytes; see Table 124. The array has 15 entries. HD line counter. The system will repeat the pattern described in `HLT' HLC times and then start with the next entry in line count array. HD line type pointer. If not 0, the value points into the line type array, index HLT - 1 with the description of the current line. 0 means the entry is not used.
HLC HLT
Table 124 Layout of the data bytes in the line count array BYTE 0 1 HLC7 HLT3 HLC6 HLT2 HLC5 HLT1 DESCRIPTION HLC4 HLT0 HLC3 0 HLC2 0 HLC1 HLC9 HLC0 HLC8
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Philips Semiconductors
Product specification
HD-CODEC
Table 125 Subaddress D1H DATA BYTE HLTA DESCRIPTION
SAA7108AE; SAA7109AE
RAM start address for the HD sync line type array; the byte following subaddress D1 points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. Each line type array entry consists of 4 bytes; see Table 126. The array has 15 entries. HD line type; if not 0, the value points into the line pattern array. The index used is HLP - 1. It consists of value-duration pairs. Each entry consists of 8 pointers, used from index 0 to 7. The value 0 means that the entry is not used.
HLP
Table 126 Layout of the data bytes in the line type array BYTE 0 1 2 3 0 0 0 0 HLP12 HLP32 HLP52 HLP72 HLP11 HLP31 HLP51 HLP71 DESCRIPTION HLP10 HLP30 HLP50 HLP70 0 0 0 0 HLP02 HLP22 HLP42 HLP62 HLP01 HLP21 HLP41 HLP61 HLP00 HLP20 HLP40 HLP60
Table 127 Subaddress D2H DATA BYTE HLPA DESCRIPTION RAM start address for the HD sync line pattern array; the byte following subaddress D2 points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. Each line pattern array entry consists of 4 value-duration pairs occupying 2 bytes; see Table 128. The array has 7 entries. HD pattern duration. The value defines the time in pixel clocks (HPD + 1) the corresponding value HPV is added to the HD output signal. If 0, this entry will be skipped. HD pattern value pointer. This gives the index in the HD value array containing the level to be inserted into the HD output path. If the MSB of HPV is logic 1, the value will only be inserted into the y/green channel of the HD data path, the other channels remain unchanged.
HPD HPV
Table 128 Layout of the data bytes in the line pattern array BYTE 0 1 2 3 4 5 6 7 HPD07 HPV03 HPD17 HPV13 HPD27 HPV23 HPD37 HPV33 HPD06 HPV02 HPD16 HPV12 HPD26 HPV22 HPD36 HPV32 HPD05 HPV01 HPD14 HPV11 HPD25 HPV21 HPD35 HPV31 DESCRIPTION HPD04 HPV00 HPD14 HPV10 HPD24 HPV20 HPD34 HPV30 HPD03 0 HPD13 0 HPD23 0 HPD33 0 HPD02 0 HPD12 0 HPD22 0 HPD32 0 HPD01 HPD09 HPD11 HPD19 HPD21 HPD29 HPD31 HPD39 HPD00 HPD08 HPD10 HPD18 HPD20 HPD28 HPD30 HPD38
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Philips Semiconductors
Product specification
HD-CODEC
Table 129 Subaddress D3H DATA BYTE HPVA DESCRIPTION
SAA7108AE; SAA7109AE
RAM start address for the HD sync value array; the byte following subaddress D3 points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. Each line pattern array entry consists of 2 bytes. The array has 8 entries. HD pattern value entry. The HD path will insert a level of (HPV + 52) x 0.66 IRE into the data path. The value is signed 8-bits wide; see Table 130. HD horizontal sync. If the HD engine is active, this value will be provided at pin HSM; see Table 130. HD vertical sync. If the HD engine is active, this value will be provided at pin VSM; see Table 130.
HPVE HHS HVS
Table 130 Layout of the data bytes in the value array BYTE 0 1 HPVE7 0 HPVE6 0 HPVE5 0 DESCRIPTION HPVE4 0 HPVE3 0 HPVE2 0 HPVE1 HVS HPVE0 HHS
Table 131 Subaddresses D4H and D5H DATA BYTE HLCT HLCPT HLPPT DESCRIPTION state of the HD line counter after trigger, note that it counts backwards state of the HD line type pointer after trigger state of the HD pattern pointer after trigger
Table 132 Subaddresses D6H and D7H DATA BYTE HDCT HEPT DESCRIPTION state of the HD duration counter after trigger, note that it counts backwards state of the HD event type pointer in the line type array after trigger
Table 133 Subaddresses D8H and D9H DATA BYTE HTX DESCRIPTION horizontal trigger phase for the HD sync engine in pixel clocks
Table 134 Subaddresses DAH and DBH DATA BYTE HTY DESCRIPTION vertical trigger phase for the HD sync engine in input lines
Table 135 Subaddress DCH DATA BYTE HDSYE HDTC LOGIC LEVEL 0 1 0 1 the HD sync engine is active HD output path processes RGB; default after reset HD output path processes YUV DESCRIPTION the HD sync engine is off; default after reset
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
DATA BYTE HDGY
LOGIC LEVEL 0 1
DESCRIPTION gain in the HD output path is reduced, insertion of sync pulses is possible; default after reset full level swing at the input causes full level swing at the DACs in HD mode interpolator for the colour difference signal in the HD output path is active; default after reset interpolator for the colour difference signals in the HD output path is off
HDIP
0 1
Table 136 Subaddresses F0H to F2H DATA BYTE CC1R, CC1G and CC1B DESCRIPTION RED, GREEN and BLUE portion of first cursor colour
Table 137 Subaddresses F3H to F5H DATA BYTE CC2R, CC2G and CC2B DESCRIPTION RED, GREEN and BLUE portion of second cursor colour
Table 138 Subaddresses F6H to F8H DATA BYTE AUXR, AUXG and AUXB DESCRIPTION RED, GREEN and BLUE portion of auxiliary cursor colour
Table 139 Subaddresses F9H and FAH DATA BYTE XCP horizontal cursor position DESCRIPTION
Table 140 Subaddress FAH DATA BYTE XHS horizontal hot spot of cursor DESCRIPTION
Table 141 Subaddresses FBH and FCH DATA BYTE YCP vertical cursor position DESCRIPTION
Table 142 Subaddress FCH DATA BYTE YHS vertical hot spot of cursor DESCRIPTION
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Philips Semiconductors
Product specification
HD-CODEC
Table 143 Subaddress FDH DATA BYTE LUTOFF CMODE LUTL IF LOGIC LEVEL 0 1 0 1 0 1 0 1 2 3 4 5 6 MATOFF DFOFF 0 1 0 1 colour look-up table is active colour look-up table is bypassed cursor mode; input colour will be inverted auxiliary cursor colour will be inserted LUT loading via input data stream is inactive
SAA7108AE; SAA7109AE
DESCRIPTION
colour and cursor LUTs are loaded via input data stream input format is 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR input format is 5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB input format is 5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB input format is 8 + 8 + 8-bit 4 : 2 : 2 non-interlaced CB-Y-CR input format is 8 + 8 + 8-bit 4 : 2 : 2 interlaced CB-Y-CR (ITU-R BT.656, 27 MHz clock) (in subaddresses 91H and 94H set XPIX = number of active pixels/line) input format is 8-bit non-interlaced index colour input format is 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR (special bit ordering) RGB to CR-Y-CB matrix is active RGB to CR-Y-CB matrix is bypassed down formatter (4 : 4 : 4 to 4 : 2 : 2) in input path is active down formatter is bypassed
Table 144 Subaddress FEH DATA BYTE CURSA DESCRIPTION RAM start address for cursor bit map; the byte following subaddress FEH points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition
Table 145 Subaddress FFH DATA BYTE COLSA DESCRIPTION RAM start address for colour LUT; the byte following subaddress FFH points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition
In subaddresses 5BH, 5CH, 5DH, 5EH, 62H and D3H all IRE values are rounded up.
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Philips Semiconductors
Product specification
HD-CODEC
18.1.3 SLAVE TRANSMITTER
SAA7108AE; SAA7109AE
Table 146 Slave transmitter (slave address 89H) REGISTER FUNCTION Status byte Chip ID FIFO status DATA BYTE SUBADDRESS D7 00H 1CH 80H VER2 CID7 0 D6 VER1 CID6 0 D5 VER0 CID5 0 D4 CCRDO CID4 0 D3 CCRDE CID3 0 D2 0 CID2 0 D1 FSEQ CID1 OVFL D0 O_E CID0 UDFL
Table 147 Subaddress 00H DATA BYTE VER CCRDO LOGIC LEVEL - 1 0 CCRDE 1 0 FSEQ O_E 1 0 1 0 Table 148 Subaddress 1CH DATA BYTE CID DESCRIPTION chip ID of SAA7108AE = 04H; chip ID of SAA7109AE = 05H DESCRIPTION version identification of the device: it will be changed with all versions of the IC that have different programming models; current version is 101 binary Closed Caption bytes of the odd field have been encoded the bit is reset after information has been written to the subaddresses 67H and 68H; it is set immediately after the data has been encoded Closed Caption bytes of the even field have been encoded the bit is reset after information has been written to the subaddresses 69H and 6AH; it is set immediately after the data has been encoded during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields) not first field of a sequence during even field during odd field
Table 149 Subaddress 80H DATA BYTE IFERR BFERR OVFL UDFL LOGIC LEVEL 0 1 0 1 0 1 0 1 normal FIFO state input FIFO overflow/underflow has occurred normal FIFO state buffer FIFO overflow, only if YUPSC = 1 no FIFO overflow FIFO overflow has occurred; this bit is reset after this subaddress has been read no FIFO underflow FIFO underflow has occurred; this bit is reset after this subaddress has been read DESCRIPTION
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Philips Semiconductors
Product specification
HD-CODEC
18.2 18.2.1 Digital video decoder part I2C-BUS FORMAT
SAA7108AE; SAA7109AE
S
SLAVE ADDRESS W
ACK-s
SUBADDRESS
ACK-s
DATA data transferred (n bytes + acknowledge)
ACK-s
P
MHB339
a. Write procedure.
S Sr
SLAVE ADDRESS W SLAVE ADDRESS R
ACK-s ACK-s
SUBADDRESS DATA
ACK-s ACK-m P
data transferred (n bytes + acknowledge)
MHB340
b. Read procedure (combined).
Fig.58 I2C-bus format.
Table 150 Description of I2C-bus format; note 1 CODE S Sr SLAVE ADDRESS W SLAVE ADDRESS R ACK-s ACK-m SUBADDRESS DATA P X Notes 1. The SAA7108AE; SAA7109AE supports the `fast mode' I2C-bus specification extension (data rate up to 400 kbits/s). 2. If pin RTCO is strapped to VDDD via a 3.3 k resistor. START condition repeated START condition `0100 0010' (42H, default) or `0100 0000' (40H; note 2) `0100 0011' (43H, default) or `0100 0001' (41H; note 2) acknowledge generated by the slave acknowledge generated by the master subaddress byte; see Tables 151 and 152 data byte; see Table 152; if more than one byte DATA is transmitted the subaddress pointer is automatically incremented STOP condition read/write control bit (LSB slave address); X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave transmitter) DESCRIPTION
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Philips Semiconductors
Product specification
HD-CODEC
Table 151 Subaddress description and access SUBADDRESS 00H F0H to FFH chip version reserved DESCRIPTION
SAA7108AE; SAA7109AE
ACCESS (READ/WRITE) read only - read and write read and write - read only - read and write - read and write - read only - read and write read and write read and write
Video decoder: 01H to 2FH 01H to 05H 06H to 19H 1AH to 1EH 1FH 20H to 2FH front-end part decoder part reserved video decoder status byte reserved
Audio clock generation: 30H to 3FH 30H to 3AH 3BH to 3FH audio clock generator reserved
General purpose VBI data slicer: 40H to 7FH 40H to 5EH 5FH 60H to 62H 63H to 7FH VBI data slicer reserved VBI data slicer status reserved
X port, I port and the scaler: 80H to EFH 80H to 8FH 90H to BFH C0H to EFH task independent global settings task A definition task B definition
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HD-CODEC
REGISTER FUNCTION Chip version: register 00H Chip version (read only)
SUB ADDR. (HEX)
D7
D6
D5
D4
D3
D2
D1
D0
00
ID7
ID6
ID5
ID4
-
-
-
-
Video decoder: registers 01H to 2FH FRONT-END PART: REGISTERS 01H TO 05H Increment delay Analog input control 1 Analog input control 2 Analog input control 3 Analog input control 4 01 02 03 04 05
(1) (1) (1) (1)
IDEL3 MODE3 HOLDG GAI13 GAI23
IDEL2 MODE2 GAFIX GAI12 GAI22
IDEL1 MODE1 GAI28 GAI11 GAI21
IDEL0 MODE0 GAI18 GAI10 GAI20
FUSE1
(1)
FUSE0 HLNRS GAI16 GAI26
GUDL1 VBSL GAI15 GAI25
GUDL0 WPOFF GAI14 GAI24
GAI17 GAI27
DECODER PART: REGISTERS 06H TO 2FH Horizontal sync start Horizontal sync stop Sync control Luminance control Luminance brightness control Luminance contrast control Chrominance saturation control Chrominance hue control Chrominance control 1 Chrominance gain control Chrominance control 2 Mode/delay control RT signal control RT/X port output control Analog/ADC/compatibility control VGATE start, FID change VGATE stop 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 HSB7 HSS7 AUFD BYPS DBRI7 DCON7 DSAT7 HUEC7 CDTO ACGC OFFU1 COLO RTSE13 RTCE CM99 VSTA7 VSTO7 HSB6 HSS6 FSEL YCOMB DBRI6 DCON6 DSAT6 HUEC6 CSTD2 CGAIN6 OFFU0 RTP1 RTSE12 XRHS UPTCV VSTA6 VSTO6 HSB5 HSS5 FOET LDEL DBRI5 DCON5 DSAT5 HUEC5 CSTD1 CGAIN5 OFFV1 HDEL1 RTSE11 XRVS1 AOSL1 VSTA5 VSTO5 HSB4 HSS4 HTC1 LUBW DBRI4 DCON4 DSAT4 HUEC4 CSTD0 CGAIN4 OFFV0 HDEL0 RTSE10 XRVS0 AOSL0 VSTA4 VSTO4 HSB3 HSS3 HTC0 LUFI3 DBRI3 DCON3 DSAT3 HUEC3 DCVF CGAIN3 CHBW RTP0 RTSE03 HLSEL XTOUTE VSTA3 VSTO3 HSB2 HSS2 HPLL LUFI2 DBRI2 DCON2 DSAT2 HUEC2 FCTC CGAIN2 LCBW2 YDEL2 RTSE02 OFTS2 OLDSB VSTA2 VSTO2 HSB1 HSS1 VNOI1 LUFI1 DBRI1 DCON1 DSAT1 HUEC1
(1)
HSB0 HSS0 VNOI0 LUFI0 DBRI0 DCON0 DSAT0
SAA7108AE; SAA7109AE
HUEC0 CCOMB CGAIN0 LCBW0 YDEL0 RTSE00 OFTS0 APCK0 VSTA0 VSTO0
CGAIN1 LCBW1 YDEL1 RTSE01 OFTS1 APCK1 VSTA1 VSTO1
Product specification
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HD-CODEC
REGISTER FUNCTION Miscellaneous, VGATE configuration and MSBs Raw data gain control Raw data offset control Reserved Status byte video decoder (read only, OLDSB = 0) Status byte video decoder (read only, OLDSB = 1) Reserved
D7 LLCE RAWG7 RAWO7
(1)
D6 LLC2E RAWG6 RAWO6
(1)
D5
(1)
D4
(1)
D3
(1)
D2 VGPS RAWG2 RAWO2
(1)
D1 VSTO8 RAWG1 RAWO1
(1)
D0 VSTA8 RAWG0 RAWO0
(1)
RAWG5 RAWO5
(1)
RAWG4 RAWO4
(1)
RAWG3 RAWO3
(1)
INTL INTL
(1)
HLVLN HLCK
(1)
FIDT FIDT
(1)
GLIMT GLIMT
(1)
GLIMB GLIMB
(1)
WIPA WIPA
(1)
COPRO SLTCA
(1)
RDCAP CODE
(1)
Audio clock generator part: registers 30H to 3FH Audio master clock cycles per field 30 31 32 Reserved Audio master clock nominal increment 33 34 35 36 Reserved Clock ratio AMXCLK to ASCLK Clock ratio ASCLK to ALRCLK Audio clock generator basic set-up Reserved 37 38 39 3A 3B to 3F ACPF7 ACPF15
(1) (1)
ACPF6 ACPF14
(1) (1)
ACPF5 ACPF13
(1) (1)
ACPF4 ACPF12
(1) (1)
ACPF3 ACPF11
(1) (1)
ACPF2 ACPF10
(1) (1)
ACPF1 ACPF9 ACPF17
(1)
ACPF0 ACPF8 ACPF16
(1)
ACNI7 ACNI15
(1) (1) (1) (1) (1)
ACNI6 ACNI14
(1) (1) (1) (1) (1)
ACNI5 ACNI13 ACNI21
(1)
ACNI4 ACNI12 ACNI20
(1)
ACNI3 ACNI11 ACNI19
(1)
ACNI2 ACNI10 ACNI18
(1)
ACNI1 ACNI9 ACNI17
(1)
ACNI0 ACNI8 ACNI16
(1)
SAA7108AE; SAA7109AE
SDIV5 LRDIV5
(1)
SDIV4 LRDIV4
(1)
SDIV3 LRDIV3 APLL
(1)
SDIV2 LRDIV2 AMVR
(1)
SDIV1 LRDIV1 LRPH
(1)
SDIV0 LRDIV0 SCPH
(1)
(1)
(1)
(1)
(1)
General purpose VBI data slicer part: registers 40H to 7FH Slicer control 1 LCR2 to LCR24 (n = 2 to 24) Programmable framing code Horizontal offset for slicer Vertical offset for slicer 40 41 to 57 58 59 5A
(1)
HAM_N LCRn_6 FC6 HOFF6 VOFF6
FCE LCRn_5 FC5 HOFF5 VOFF5
HUNT_N LCRn_4 FC4 HOFF4 VOFF4
(1)
(1)
(1)
(1)
Product specification
LCRn_7 FC7 HOFF7 VOFF7
LCRn_3 FC3 HOFF3 VOFF3
LCRn_2 FC2 HOFF2 VOFF2
LCRn_1 FC1 HOFF1 VOFF1
LCRn_0 FC0 HOFF0 VOFF0
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HD-CODEC
REGISTER FUNCTION Field offset and MSBs for horizontal and vertical offset Reserved (for testing) Header and data identification (DID) code control Sliced data identification (SDID) code Reserved Slicer status byte 0 (read only) Slicer status byte 1 (read only) Slicer status byte 2 (read only) Reserved
D7 FOFF
(1)
D6 RECODE
(1) (1)
D5
(1)
D4 VOFF8
(1)
D3
(1)
D2 HOFF10
(1)
D1 HOFF9
(1)
D0 HOFF8
(1)
(1)
(1)
FVREF
(1)
DID5 SDID5
(1)
DID4 SDID4
(1)
DID3 SDID3
(1)
DID2 SDID2
(1)
DID1 SDID1
(1)
DID0 SDID0
(1)
(1)
(1)
(1)
- - LN3
(1)
FC8V - LN2
(1)
FC7V F21_N LN1
(1)
VPSV LN8 LN0
(1)
PPV LN7 DT3
(1)
CCV LN6 DT2
(1)
- LN5 DT1
(1)
- LN4 DT0
(1)
X port, I port and the scaler part: registers 80H to EFH TASK INDEPENDENT GLOBAL SETTINGS: 80H TO 8FH Global control 1 Reserved X port I/O enable and output clock phase control I port signal definitions I port signal polarities I port FIFO flag control and arbitration I port I/O enable, output clock and gated clock phase control Power save control Reserved Status information scaler part 80 81 and 82 83 84 85 86 87 88 89 to 8E 8F
(1) (1)
SMOD
(1)
TEB
(1)
TEA
(1)
ICKS3
(1)
ICKS2
(1)
ICKS1
(1)
ICKS0
(1)
(1)
(1)
XPCK1 IDG11 ILLV IDG02 IPCK1 SWRST
(1)
XPCK0 IDG10 IG0P IDG12 IPCK0 DPROG
(1)
(1)
XRQT IDV0 IRVP FFL0
(1)
XPE1 IDH1 IRHP FEL1 IPE1 SLM1
(1)
XPE0 IDH0 IDQP FEL0 IPE0 SLM0
(1)
IDG01 ISWP1 VITX1 IPCK3 CH4EN
(1)
IDG00 ISWP0 VITX0 IPCK2 CH2EN
(1)
IDV1 IG1P FFL1
(1)
SAA7108AE; SAA7109AE
SLM3
(1)
(1) (1)
Product specification
XTRI
ITRI
FFIL
FFOV
PRDON
ERROF
FIDSCI
FIDSCO
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HD-CODEC
REGISTER FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
TASK A DEFINITION: REGISTERS 90H TO BFH
Basic settings and acquisition window definition
Task handling control X port formats and configuration X port input reference signal definitions I port output formats and configuration Horizontal input window start Horizontal input window length Vertical input window start Vertical input window length Horizontal output window length Vertical output window length 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F CONLH CONLV XFDV ICODE XO7
(1)
OFIDC HLDFV XFDH I8_16 XO6
(1)
FSKP2 SCSRC1 XDV1 FYSK XO5
(1)
FSKP1 SCSRC0 XDV0 FOI1 XO4
(1)
FSKP0 SCRQE XCODE FOI0 XO3 XO11 XS3 XS11 YO3 YO11 YS3 YS11 XD3 XD11 YD3 YD11
RPTSK FSC2 XDH FSI2 XO2 XO10 XS2 XS10 YO2 YO10 YS2 YS10 XD2 XD10 YD2 YD10
STRC1 FSC1 XDQ FSI1 XO1 XO9 XS1 XS9 YO1 YO9 YS1 YS9 XD1 XD9 YD1 YD9
STRC0 FSC0 XCKS FSI0 XO0 XO8 XS0 XS8 YO0 YO8 YS0 YS8 XD0 XD8 YD0 YD8
XS7
(1)
XS6
(1)
XS5
(1)
XS4
(1)
YO7
(1)
YO6
(1)
YO5
(1)
YO4
(1)
YS7
(1)
YS6
(1)
YS5
(1)
YS4
(1)
XD7
(1)
XD6
(1)
XD5
(1)
XD4
(1)
YD7
(1)
YD6
(1)
YD5
(1)
YD4
(1)
SAA7108AE; SAA7109AE
FIR filtering and prescaling
Horizontal prescaling Accumulation length Prescaler DC gain and FIR prefilter control Reserved Luminance brightness control Luminance contrast control Chrominance saturation control Reserved A0 A1 A2 A3 A4 A5 A6 A7
(1) (1) (1) (1)
XPSC5 XACL5 PFY1
(1)
XPSC4 XACL4 PFY0
(1)
XPSC3 XACL3 XC2_1
(1)
XPSC2 XACL2 XDCG2
(1)
XPSC1 XACL1 XDCG1
(1)
XPSC0 XACL0 XDCG0
(1)
PFUV1
(1)
PFUV0
(1)
Product specification
BRIG7 CONT7 SATN7
(1)
BRIG6 CONT6 SATN6
(1)
BRIG5 CONT5 SATN5
(1)
BRIG4 CONT4 SATN4
(1)
BRIG3 CONT3 SATN3
(1)
BRIG2 CONT2 SATN2
(1)
BRIG1 CONT1 SATN1
(1)
BRIG0 CONT0 SATN0
(1)
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HD-CODEC
REGISTER FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
Horizontal phase scaling
Horizontal luminance scaling increment Horizontal luminance phase offset Reserved Horizontal chrominance scaling increment Horizontal chrominance phase offset Reserved A8 A9 AA AB AC AD AE AF XSCY7
(1)
XSCY6
(1)
XSCY5
(1)
XSCY4 XSCY12 XPHY4
(1)
XSCY3 XSCY11 XPHY3
(1)
XSCY2 XSCY10 XPHY2
(1)
XSCY1 XSCY9 XPHY1
(1)
XSCY0 XSCY8 XPHY0
(1)
XPHY7
(1)
XPHY6
(1)
XPHY5
(1)
XSCC7
(1)
XSCC6
(1)
XSCC5
(1)
XSCC4 XSCC12 XPHC4
(1)
XSCC3 XSCC11 XPHC3
(1)
XSCC2 XSCC10 XPHC2
(1)
XSCC1 XSCC9 XPHC1
(1)
XSCC0 XSCC8 XPHC0
(1)
XPHC7
(1)
XPHC6
(1)
XPHC5
(1)
Vertical scaling
Vertical luminance scaling increment Vertical chrominance scaling increment Vertical scaling mode control Reserved Vertical chrominance phase offset `00' Vertical chrominance phase offset `01' Vertical chrominance phase offset `10' Vertical chrominance phase offset `11' Vertical luminance phase offset `00' Vertical luminance phase offset `01' Vertical luminance phase offset `10' B0 B1 B2 B3 B4 B5 to B7 B8 B9 BA BB BC BD BE YSCY7 YSCY15 YSCC7 YSCC15
(1) (1)
YSCY6 YSCY14 YSCC6 YSCC14
(1) (1)
YSCY5 YSCY13 YSCC5 YSCC13
(1) (1)
YSCY4 YSCY12 YSCC4 YSCC12 YMIR
(1)
YSCY3 YSCY11 YSCC3 YSCC11
(1) (1)
YSCY2 YSCY10 YSCC2 YSCC10
(1) (1)
YSCY1 YSCY9 YSCC1 YSCC9
(1) (1)
YSCY0 YSCY8 YSCC0 YSCC8 YMODE
(1)
YPC07 YPC17 YPC27 YPC37 YPY07 YPY17 YPY27
YPC06 YPC16 YPC26 YPC36 YPY06 YPY16 YPY26
YPC05 YPC15 YPC25 YPC35 YPY05 YPY15 YPY25
YPC04 YPC14 YPC24 YPC34 YPY04 YPY14 YPY24
YPC03 YPC13 YPC23 YPC33 YPY03 YPY13 YPY23
YPC02 YPC12 YPC22 YPC32 YPY02 YPY12 YPY22
YPC01 YPC11 YPC21 YPC31 YPY01 YPY11 YPY21
YPC00 YPC10 YPC20 YPC30 YPY00 YPY10 YPY20
SAA7108AE; SAA7109AE
Product specification
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HD-CODEC
REGISTER FUNCTION Vertical luminance phase offset `11'
D7 YPY37
D6 YPY36
D5 YPY35
D4 YPY34
D3 YPY33
D2 YPY32
D1 YPY31
D0 YPY30
TASK B DEFINITION REGISTERS C0H TO EFH
Basic settings and acquisition window definition
Task handling control X port formats and configuration Input reference signal definition I port formats and configuration Horizontal input window start Horizontal input window length Vertical input window start Vertical input window length Horizontal output window length Vertical output window length C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CONLH CONLV XFDV ICODE XO7
(1)
OFIDC HLDFV XFDH I8_16 XO6
(1)
FSKP2 SCSRC1 XDV1 FYSK XO5
(1)
FSKP1 SCSRC0 XDV0 FOI1 XO4
(1)
FSKP0 SCRQE XCODE FOI0 XO3 XO11 XS3 XS11 YO3 YO11 YS3 YS11 XD3 XD11 YD3 YD11
RPTSK FSC2 XDH FSI2 XO2 XO10 XS2 XS10 YO2 YO10 YS2 YS10 XD2 XD10 YD2 YD10
STRC1 FSC1 XDQ FSI1 XO1 XO9 XS1 XS9 YO1 YO9 YS1 YS9 XD1 XD9 YD1 YD9
STRC0 FSC0 XCKS FSI0 XO0 XO8 XS0 XS8 YO0 YO8 YS0 YS8 XD0 XD8 YD0 YD8
XS7
(1)
XS6
(1)
XS5
(1)
XS4
(1)
YO7
(1)
YO6
(1)
YO5
(1)
YO4
(1)
YS7
(1)
YS6
(1)
YS5
(1)
YS4
(1)
XD7
(1)
XD6
(1)
XD5
(1)
XD4
(1)
YD7
(1)
YD6
(1)
YD5
(1)
YD4
(1)
SAA7108AE; SAA7109AE
FIR filtering and prescaling
Horizontal prescaling Accumulation length Prescaler DC gain and FIR prefilter control Reserved Luminance brightness control Luminance contrast control Chrominance saturation control Reserved D0 D1 D2 D3 D4 D5 D6 D7
(1) (1) (1) (1)
XPSC5 XACL5 PFY1
(1)
XPSC4 XACL4 PFY0
(1)
XPSC3 XACL3 XC2_1
(1)
XPSC2 XACL2 XDCG2
(1)
XPSC1 XACL1 XDCG1
(1)
XPSC0 XACL0 XDCG0
(1)
PFUV1
(1)
PFUV0
(1)
Product specification
BRIG7 CONT7 SATN7
(1)
BRIG6 CONT6 SATN6
(1)
BRIG5 CONT5 SATN5
(1)
BRIG4 CONT4 SATN4
(1)
BRIG3 CONT3 SATN3
(1)
BRIG2 CONT2 SATN2
(1)
BRIG1 CONT1 SATN1
(1)
BRIG0 CONT0 SATN0
(1)
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HD-CODEC
REGISTER FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
Horizontal phase scaling
Horizontal luminance scaling increment Horizontal luminance phase offset Reserved Horizontal chrominance scaling increment Horizontal chrominance phase offset Reserved D8 D9 DA DB DC DD DE DF XSCY7
(1)
XSCY6
(1)
XSCY5
(1)
XSCY4 XSCY12 XPHY4
(1)
XSCY3 XSCY11 XPHY3
(1)
XSCY2 XSCY10 XPHY2
(1)
XSCY1 XSCY9 XPHY1
(1)
XSCY0 XSCY8 XPHY0
(1)
XPHY7
(1)
XPHY6
(1)
XPHY5
(1)
XSCC7
(1)
XSCC6
(1)
XSCC5
(1)
XSCC4 XSCC12 XPHC4
(1)
XSCC3 XSCC11 XPHC3
(1)
XSCC2 XSCC10 XPHC2
(1)
XSCC1 XSCC9 XPHC1
(1)
XSCC0 XSCC8 XPHC0
(1)
XPHC7
(1)
XPHC6
(1)
XPHC5
(1)
Vertical scaling
Vertical luminance scaling increment Vertical chrominance scaling increment Vertical scaling mode control Reserved Vertical chrominance phase offset `00' Vertical chrominance phase offset `01' Vertical chrominance phase offset `10' Vertical chrominance phase offset `11' Vertical luminance phase offset `00' E0 E1 E2 E3 E4 E5 to E7 E8 E9 EA EB EC YSCY7 YSCY15 YSCC7 YSCC15
(1) (1)
YSCY6 YSCY14 YSCC6 YSCC14
(1) (1)
YSCY5 YSCY13 YSCC5 YSCC13
(1) (1)
YSCY4 YSCY12 YSCC4 YSCC12 YMIR
(1)
YSCY3 YSCY11 YSCC3 YSCC11
(1) (1)
YSCY2 YSCY10 YSCC2 YSCC10
(1) (1)
YSCY1 YSCY9 YSCC1 YSCC9
(1) (1)
YSCY0 YSCY8 YSCC0 YSCC8 YMODE
(1)
YPC07 YPC17 YPC27 YPC37 YPY07
YPC06 YPC16 YPC26 YPC36 YPY06
YPC05 YPC15 YPC25 YPC35 YPY05
YPC04 YPC14 YPC24 YPC34 YPY04
YPC03 YPC13 YPC23 YPC33 YPY03
YPC02 YPC12 YPC22 YPC32 YPY02
YPC01 YPC11 YPC21 YPC31 YPY01
YPC00 YPC10 YPC20 YPC30 YPY00
SAA7108AE; SAA7109AE
Product specification
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HD-CODEC
REGISTER FUNCTION Vertical luminance phase offset `01' Vertical luminance phase offset `10' Vertical luminance phase offset `11' Note
D7 YPY17 YPY27 YPY37
D6 YPY16 YPY26 YPY36
D5 YPY15 YPY25 YPY35
D4 YPY14 YPY24 YPY34
D3 YPY13 YPY23 YPY33
D2 YPY12 YPY22 YPY32
D1 YPY11 YPY21 YPY31
D0 YPY10 YPY20 YPY30
1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. 18.2.2 I2C-BUS DETAIL
18.2.2.1
Subaddress 00H
Table 153 Chip version (CV) identification; 00H[7:4]; read only register LOGIC LEVELS FUNCTION ID7 CV3 ID6 CV2 ID5 CV1 ID4 CV0
18.2.2.2
Subaddress 01H
The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position only.
SAA7108AE; SAA7109AE
Table 154 Horizontal increment delay; 01H[3:0] FUNCTION No update Minimum delay Recommended position Maximum delay IDEL3 1 1 1 0 IDEL2 1 1 0 0 IDEL1 1 1 0 0 IDEL0 1 0 0 0
Product specification
Philips Semiconductors
Product specification
HD-CODEC
18.2.2.3 Subaddress 02H
SAA7108AE; SAA7109AE
Table 155 Analog input control 1 (AICO1); 02H[7:0] BIT DESCRIPTION SYMBOL FUSE[1:0] VALUE 00 01 10 11 5 and 4 update hysteresis for 9-bit gain; see Fig.16 GUDL[1:0] 00 01 10 11 3 to 0 mode selection MODE[3:0] 0000 0001 0010 0011 0100 0101 0110 amplifier active amplifier plus anti-alias filter active off 1 LSB 2 LSB 3 LSB Mode 0: CVBS (automatic gain) from AI11 (pin P13); see Fig.59 Mode 1: CVBS (automatic gain) from AI12 (pin P11); see Fig.60 Mode 2: CVBS (automatic gain) from AI21 (pin P10); see Fig.61 Mode 3: CVBS (automatic gain) from AI22 (pin P9); see Fig.62 Mode 4: CVBS (automatic gain) from AI23 (pin P7); see Fig.63 Mode 5: CVBS (automatic gain) from AI24 (pin P6); see Fig.64 Mode 6: Y (automatic gain) from AI11 (pin P13) + C (gain adjustable via GAI28 to GAI20) from AI21 (pin P10); note 1; see Fig.65 Mode 7: Y (automatic gain) from AI12 (pin P11) + C (gain adjustable via GAI28 to GAI20) from AI22 (pin P9); note 1; see Fig.66 Mode 8: Y (automatic gain) from AI11 (pin P13) + C (gain adapted to Y gain) from AI21 (pin P10); note 1; see Fig.67 Mode 9: Y (automatic gain) from AI12 (pin P11) + C (gain adapted to Y gain) from AI22 (pin P9); note 1; see Fig.68 Modes 10 to 15: reserved FUNCTION amplifier plus anti-alias filter bypassed
7 and 6 analog function select; see Fig.15
0111
1000 1001 1010 to 1111 Note
1. To take full advantage of the Y/C modes 6 to 9 the I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth).
2004 Jun 29
146
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
AI24 AI23 AI22 AI21 AI12 AI11
AD2
CHROMA
AI24 AI23 AI22 AI21 AI12 AI11
AD2
CHROMA
AD1
LUMA
MHB559
AD1
LUMA
MHB560
Fig.59 Mode 0; CVBS (automatic gain).
Fig.60 Mode 1; CVBS (automatic gain).
AI24 AI23 AI22 AI21 AI12 AI11
AD2
CHROMA
AI24 AI23 AI22 AI21 AI12 AI11
AD2
CHROMA
AD1
LUMA
MHB561
AD1
LUMA
MHB562
Fig.61 Mode 2; CVBS (automatic gain).
Fig.62 Mode 3; CVBS (automatic gain).
AI24 AI23 AI22 AI21 AI12 AI11
AD2
CHROMA
AI24 AI23 AI22 AI21 AI12 AI11
AD2
CHROMA
AD1
LUMA
MHB563
AD1
LUMA
MHB564
Fig.63 Mode 4; CVBS (automatic gain).
Fig.64 Mode 5; CVBS (automatic gain).
2004 Jun 29
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
AI24 AI23 AI22 AI21 AI12 AI11
AD2
CHROMA
AI24 AI23 AI22 AI21 AI12 AI11
AD2
CHROMA
AD1
LUMA
MHB565
AD1
LUMA
MHB566
I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth).
I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth).
Fig.65 Mode 6; Y + C (gain channel 2 adjusted via GAI2).
Fig.66 Mode 7; Y + C (gain channel 2 adjusted via GAI2).
AI24 AI23 AI22 AI21 AI12 AI11
AD2
CHROMA
AI24 AI23 AI22 AI21 AI12 AI11
AD2
CHROMA
AD1
LUMA
MHB567
AD1
LUMA
MHB568
I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth).
I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth).
Fig.67 Mode 8; Y + C (gain channel 2 adapted to Y gain).
Fig.68 Mode 9; Y + C (gain channel 2 adapted to Y gain).
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Philips Semiconductors
Product specification
HD-CODEC
18.2.2.4 Subaddress 03H
SAA7108AE; SAA7109AE
Table 156 Analog input control 2 (AICO2); 03H[6:0] BIT 6 5 DESCRIPTION HL not reference select AGC hold during vertical blanking period SYMBOL VALUE HLNRS VBSL 0 1(1) 0 1 FUNCTION normal clamping if decoder is in unlocked state reference select if decoder is in unlocked state short vertical blanking (AGC disabled during equalization and serration pulses) long vertical blanking (AGC disabled from start of pre-equalization pulses until start of active video (line 22 for 60 Hz, line 24 for 50 Hz) white peak control active white peak control off AGC active AGC integration hold (freeze) automatic gain controlled by MODE3 to MODE0 gain is user programmable via GAI[17:10] and GAI[27:20] see Table 158 see Table 157
4 3 2 1 0 Note
white peak control off automatic gain control integration gain control fix static gain control channel 2 sign bit static gain control channel 1 sign bit
WPOFF HOLDG GAFIX GAI28 GAI18
0(1) 1 0 1 0 1
1. HLNRS = 1 should not be used in combination with WPOFF = 0.
18.2.2.5
Subaddress 04H
Table 157 Analog input control 3 (AICO3); static gain control channel 1; 03H[0] and 04H[7:0] DECIMAL VALUE 0... ...144 145... ...511 GAIN (dB) -3 0 0 +6 SIGN BIT 03H[0] GAI18 0 0 0 1 GAI17 0 1 1 1 GAI16 0 0 0 1 CONTROL BITS 7 TO 0 GAI15 0 0 0 1 GAI14 0 1 1 1 GAI13 0 0 0 1 GAI12 0 0 0 1 GAI11 0 0 0 1 GAI10 0 0 1 1
18.2.2.6
Subaddress 05H
Table 158 Analog input control 4 (AICO4); static gain control channel 2; 03H[1] and 05H[7:0] DECIMAL VALUE 0... ...144 145... ...511 2004 Jun 29 GAIN (dB) -3 0 0 +6 SIGN BIT 03H[1] GAI28 0 0 0 1 GAI27 0 1 1 1 GAI26 0 0 0 1 149 CONTROL BITS 7 TO 0 GAI25 0 0 0 1 GAI24 0 1 1 1 GAI23 0 0 0 1 GAI22 0 0 0 1 GAI21 0 0 0 1 GAI20 0 0 1 1
Philips Semiconductors
Product specification
HD-CODEC
18.2.2.7 Subaddress 06H
SAA7108AE; SAA7109AE
Table 159 Horizontal sync start; 06H[7:0] DELAY TIME (STEP SIZE = 8/LLC) -128...-109 (50 Hz) -128...-108 (60 Hz) -108 (50 Hz)... -107 (60 Hz)... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 1 CONTROL BITS 7 TO 0 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0
forbidden (outside available central counter range)
forbidden (outside available central counter range)
18.2.2.8
Subaddress 07H
Table 160 Horizontal sync stop; 07H[7:0] DELAY TIME (STEP SIZE = 8/LLC) -128...-109 (50 Hz) -128...-108 (60 Hz) -108 (50 Hz)... -107 (60 Hz)... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 1 CONTROL BITS 7 TO 0 HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0
forbidden (outside available central counter range)
forbidden (outside available central counter range)
2004 Jun 29
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Philips Semiconductors
Product specification
HD-CODEC
18.2.2.9 Subaddress 08H
SAA7108AE; SAA7109AE
Table 161 Sync control; 08H[7:0] BIT 7 6 5 DESCRIPTION automatic field detection field selection forced ODD/EVEN toggle SYMBOL VALUE AUFD FSEL FOET 0 1 0 1 0 1 HTC[1:0] 00 01 10 11 2 horizontal PLL HPLL VNOI[1:0] 0 1 1 and 0 vertical noise reduction 00 01 10 11 FUNCTION field state directly controlled via FSEL automatic field detection; recommended setting 50 Hz, 625 lines 60 Hz, 525 lines ODD/EVEN signal toggles only with interlaced source ODD/EVEN signal toggles fieldwise even if source is non-interlaced TV mode, recommended for poor quality TV signals only; do not use for new applications VTR mode, recommended if a deflection control circuit is directly connected to the SAA7108AE; SAA7109AE reserved fast locking mode; recommended setting PLL closed PLL open; horizontal frequency fixed normal mode; recommended setting fast mode, applicable for stable sources only; automatic field detection (AUFD) must be disabled free running mode vertical noise reduction bypassed
4 and 3 horizontal time constant selection
2004 Jun 29
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Philips Semiconductors
Product specification
HD-CODEC
18.2.2.10 Subaddress 09H
Table 162 Luminance control; 09H[7:0] BIT 7 DESCRIPTION chrominance trap/comb filter bypass SYMBOL BYPS VALUE 0 1 6 5 adaptive luminance comb filter processing delay in non comb filter mode remodulation bandwidth for luminance; see Figs 21 to 24 sharpness control, luminance filter characteristic; see Fig.25 YCOMB LDEL 0 1 0 1 LUBW 0 1 LUFI[3:0] 0001 0010 0011 0100 0101 0110 0111 0000 1000 1001 1010 1011 1100 1101 1110 1111
SAA7108AE; SAA7109AE
FUNCTION chrominance trap or luminance comb filter active; default for CVBS mode chrominance trap or luminance comb filter bypassed; default for S-video mode disabled (= chrominance trap enabled, if BYPS = 0) active, if BYPS = 0 processing delay is equal to internal pipelining delay one (NTSC standards) or two (PAL standards) video lines additional processing delay small remodulation bandwidth (narrow chrominance notch higher luminance bandwidth) large remodulation bandwidth (wider chrominance notch smaller luminance bandwidth) resolution enhancement filter; 8.0 dB at 4.1 MHz resolution enhancement filter; 6.8 dB at 4.1 MHz resolution enhancement filter; 5.1 dB at 4.1 MHz resolution enhancement filter; 4.1 dB at 4.1 MHz resolution enhancement filter; 3.0 dB at 4.1 MHz resolution enhancement filter; 2.3 dB at 4.1 MHz resolution enhancement filter; 1.6 dB at 4.1 MHz plain low-pass filter; 2 dB at 4.1 MHz low-pass filter; 3 dB at 4.1 MHz low-pass filter; 3 dB at 3.3 MHz; 4 dB at 4.1 MHz low-pass filter; 3 dB at 2.6 MHz; 8 dB at 4.1 MHz low-pass filter; 3 dB at 2.4 MHz; 14 dB at 4.1 MHz low-pass filter; 3 dB at 2.2 MHz; notch at 3.4 MHz low-pass filter; 3 dB at 1.9 MHz; notch at 3.0 MHz low-pass filter; 3 dB at 1.7 MHz; notch at 2.5 MHz
4
3 to 0
18.2.2.11 Subaddress 0AH
Table 163 Luminance brightness control: decoder part; 0AH[7:0] CONTROL BITS 7 TO 0 OFFSET DBRI7 255 (bright) 128 (ITU level) 0 (dark) 1 1 0 DBRI6 1 0 0 DBRI5 1 0 0 DBRI4 1 0 0 DBRI3 1 0 0 DBRI2 1 0 0 DBRI1 1 0 0 DBRI0 1 0 0
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Philips Semiconductors
Product specification
HD-CODEC
18.2.2.12 Subaddress 0BH
Table 164 Luminance contrast control: decoder part; 0BH[7:0]
SAA7108AE; SAA7109AE
CONTROL BITS 7 TO 0 GAIN DCON7 1.984 (maximum) 1.063 (ITU level) 1.0 0 (luminance off) -1 (inverse luminance) -2 (inverse luminance) 0 0 0 0 1 1 DCON6 1 1 1 0 1 0 DCON5 1 0 0 0 0 0 DCON4 1 0 0 0 0 0 DCON3 1 0 0 0 0 0 DCON2 1 1 0 0 0 0 DCON1 1 0 0 0 0 0 DCON0 1 0 0 0 0 0
18.2.2.13 Subaddress 0CH
Table 165 Chrominance saturation control: decoder part; 0CH[7:0] CONTROL BITS 7 TO 0 GAIN DSAT7 1.984 (maximum) 1.0 (ITU level) 0 (colour off) -1 (inverse chrominance) -2 (inverse chrominance) 0 0 0 1 1 DSAT6 1 1 0 1 0 DSAT5 1 0 0 0 0 DSAT4 1 0 0 0 0 DSAT3 1 0 0 0 0 DSAT2 1 0 0 0 0 DSAT1 1 0 0 0 0 DSAT0 1 0 0 0 0
18.2.2.14 Subaddress 0DH
Table 166 Chrominance hue control: 0DH[7:0] CONTROL BITS 7 TO 0 HUE PHASE (DEG) HUEC7 +178.6... ...0... ...-180 0 0 1 HUEC6 1 0 0 HUEC5 1 0 0 HUEC4 1 0 0 HUEC3 1 0 0 HUEC2 1 0 0 HUEC1 1 0 0 HUEC0 1 0 0
2004 Jun 29
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Philips Semiconductors
Product specification
HD-CODEC
18.2.2.15 Subaddress 0EH
Table 167 Chrominance control 1; 0EH[7:0]
SAA7108AE; SAA7109AE
FUNCTION BIT 7 DESCRIPTION clear DTO SYMBOL CDTO VALUE 50 Hz/625 LINES 0 1 disabled Every time CDTO is set, the internal subcarrier DTO phase is reset to 0 and the RTCO output generates a logic 0 at time slot 68 (see document "RTC Functional Description", available on request). So an identical subcarrier phase can be generated by an external device (e.g. an encoder). PAL BGDHI (4.43 MHz) NTSC 4.43 (50 Hz) Combination-PAL N (3.58 MHz) NTSC N (3.58 MHz) reserved SECAM NTSC M (3.58 MHz) PAL 4.43 (60 Hz) NTSC 4.43 (60 Hz) PAL M (3.58 MHz) NTSC-Japan (3.58 MHz) reserved reserved; do not use reserved; do not use chrominance vertical filter and PAL phase error correction on (during active video lines) chrominance vertical filter and PAL phase error correction permanently off nominal time constant fast time constant for special applications disabled active 60 Hz/525 LINES
6 to 4 colour standard selection
CSTD[2:0]
000 001 010 011 100 101 110 111
3
disable chrominance vertical filter and PAL phase error correction fast colour time constant adaptive chrominance comb filter
DCVF
0 1
2 0
FCTC CCOMB
0 1 0 1
18.2.2.16 Subaddress 0FH
Table 168 Chrominance gain control; 0FH[7:0] BIT 7 DESCRIPTION automatic chrominance gain control SYMBOL ACGC VALUE 0 1 on programmable gain via CGAIN6 to CGAIN0; need to be set for SECAM standard FUNCTION
6 to 0 chrominance gain value (if ACGC is set to logic 1)
CGAIN[6:0] 000 0000 minimum gain (0.5) 010 0100 nominal gain (1.125) 111 1111 maximum gain (7.5)
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Philips Semiconductors
Product specification
HD-CODEC
18.2.2.17 Subaddress 10H
Table 169 Chrominance control 2; 10H[7:0] BIT 7 and 6 DESCRIPTION fine offset adjustment B - Y component SYMBOL OFFU[1:0]
SAA7108AE; SAA7109AE
VALUE 00 01 10 11 0 LSB
1 1 3 1 1 3 4 2 4
FUNCTION LSB LSB LSB LSB LSB LSB
5 and 4
fine offset adjustment R - Y component
OFFV[1:0]
00 01 10 11
0 LSB
4 2 4
3 2 to 0
chrominance bandwidth; see Figs 19 and 20 combined luminance/chrominance bandwidth adjustment; see Figs 19 to 25
CHBW LCBW[2:0]
0 1 000 ... 111
small wide smallest chrominance bandwidth or largest luminance bandwidth ... to ... largest chrominance bandwidth or smallest luminance bandwidth
18.2.2.18 Subaddress 11H
Table 170 Mode/delay control; 11H[7:0] BIT 7 6 5 and 4 colour on polarity of RTS1 output signal fine position of HS (steps in 2/LLC) DESCRIPTION SYMBOL COLO RTP1 HDEL[1:0] VALUE 0 1 0 1 00 01 10 11 3 2 to 0 polarity of RTS0 output signal luminance delay compensation (steps in 2/LLC) RTP0 YDEL[2:0] 0 1 100 000 011 FUNCTION automatic colour killer enabled colour forced on non inverted inverted 0 1 2 3 non inverted inverted -4... ...0... ...3
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Philips Semiconductors
Product specification
HD-CODEC
18.2.2.19 Subaddress 12H
Table 171 RT signal control: RTS0 output; 12H[3:0] The polarity of any signal on RTS0 can be inverted via RTP0[11H[3]]. RTS0 OUTPUT 3-state Constant LOW CREF (13.5 MHz toggling pulse; see Fig.32) CREF2 (6.75 MHz toggling pulse; see Fig.32) HL; horizontal lock indicator (note 1): HL = 0: unlocked HL = 1: locked VL; vertical and horizontal lock: VL = 0: unlocked VL = 1: locked DL; vertical and horizontal lock and colour detected: DL = 0: unlocked DL = 1: locked Reserved HREF, horizontal reference signal; indicates 720 pixels valid data on the expansion port. The positive slope marks the beginning of a new active line. HREF is also generated during the vertical blanking interval; see Fig.32. HS: programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0] 07H[7:0] fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]; see Fig.32 HQ; HREF gated with VGATE Reserved V123; vertical sync; see vertical timing diagrams Figs 30 and 31 VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]] LSBs of the 9-bit ADC's FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0]; see vertical timing diagrams Figs 30 and 31 Note 1. Function of HL is selectable via HLSEL[13H[3]]: a) HLSEL = 0: HL is standard horizontal lock indicator.
SAA7108AE; SAA7109AE
RTSE03 RTSE02 RTSE01 RTSE00 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0
0
1
0
1
0
1
1
0
0 1
1 0
1 0
1 0
1
0
0
1
1 1 1 1 1 1
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. VCRs).
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Philips Semiconductors
Product specification
HD-CODEC
Table 172 RT signal control: RTS1 output; 12H[7:4] The polarity of any signal on RTS1 can be inverted via RTP1[11H[6]]. RTS1 OUTPUT CONTROL 3-state Constant LOW CREF (13.5 MHz toggling pulse; see Fig.32) CREF2 (6.75 MHz toggling pulse; see Fig.32) HL; horizontal lock indicator (note 1): HL = 0: unlocked HL = 1: locked VL; vertical and horizontal lock: VL = 0: unlocked VL = 1: locked DL; vertical and horizontal lock and colour detected: DL = 0: unlocked DL = 1: locked Reserved HREF, horizontal reference signal: indicates 720 pixels valid data on the expansion port. The positive slope marks the beginning of a new active line. HREF is also generated during the vertical blanking interval; see Fig.32. HS: programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0] 07H[7:0] fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]; see Fig.32 HQ; HREF gated with VGATE Reserved V123; vertical sync; see vertical timing diagrams Figs 30 and 31 VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]] Reserved FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0]; see vertical timing diagrams Figs 30 and 31 Note 1. Function of HL is selectable via HLSEL[13H[3]]: a) HLSEL = 0: HL is standard horizontal lock indicator.
SAA7108AE; SAA7109AE
RTSE13 RTSE12 RTSE11 RTSE10 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0
0
1
0
1
0
1
1
0
0 1
1 0
1 0
1 0
1
0
0
1
1 1 1 1 1 1
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. VCRs).
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Philips Semiconductors
Product specification
HD-CODEC
18.2.2.20 Subaddress 13H
Table 173 RT/X port output control; 13H[7:0] BIT 7 6 DESCRIPTION RTCO output enable X port XRH output selection SYMBOL RTCE XRHS VALUE 0 1 0 1 3-state enabled
SAA7108AE; SAA7109AE
FUNCTION
HREF; see Fig.32 HS: programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0] 07H[7:0] fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]; see Fig.32
5 and 4 X port XRV output selection
XRVS[1:0]
00 01 10 11
V123; see Figs 30 and 31 ITU 656 related field ID; see Figs 30 and 31 inverted V123 inverted ITU 656 related field ID copy of inverted HLCK status bit (default) fast horizontal lock indicator (for special applications only) ITU 656 ITU 656 like format with modified field blanking according to VGATE position (programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]]) Y-CB-CR 4 : 2 : 2 8-bit format (no SAV/EAV codes inserted) reserved multiplexed AD2/AD1 bypass (bits 8 to 1) dependent on mode settings; if both ADCs are selected AD2 is output at CREF = 1 and AD1 is output at CREF = 0 multiplexed AD2/AD1 bypass (bits 7 to 0) dependent on mode settings; if both ADCs are selected AD2 is output at CREF = 1 and AD1 is output at CREF = 0 reserved multiplexed ADC MSB/LSB bypass dependent on mode settings; only one ADC should be selected at a time; ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0 are outputs at CREF = 0
3 2 to 0
horizontal lock indicator selection
HLSEL
0 1 000 001
XPD7 to XPD0 (port OFTS[2:0] output format selection); see Section 10.4
010 011 100
101
110 111
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Philips Semiconductors
Product specification
HD-CODEC
18.2.2.21 Subaddress 14H
Table 174 Analog/ADC/compatibility control; 14H[7:0] BIT 7 DESCRIPTION compatibility bit for SAA7199 update time interval for AGC value SYMBOL CM99 VALUE 0 1 UPTCV AOSL[1:0] 0 1 00 01 10 11 3 2 XTOUTd output enable decoder status byte selection; see Table 180 XTOUTE OLDSB APCK[1:0] 0 1 0 1 00 01 10 11 off (default)
SAA7108AE; SAA7109AE
FUNCTION on (to be set only if SAA7199 is used for re-encoding in conjunction with RTCO active) horizontal update (once per line) vertical update (once per field) AOUT connected to internal test point 1 AOUT connected to input AD1 AOUT connected to input AD2 AOUT connected to internal test point 2 pin P4 (XTOUTd) 3-stated pin P4 (XTOUTd) enabled standard backward compatibility to SAA7112 application dependent
6
5 and 4 analog test select
1 and 0 ADC sample clock phase delay
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18.2.2.22 Subaddress 15H
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Philips Semiconductors
HD-CODEC
Table 175 VGATE start; FID polarity change; 17H[0] and 15H[7:0] Start of VGATE pulse (LOW-to-HIGH transition) and polarity change of FID pulse, VGPS = 0; see Figs 30 and 31. FRAME LINE COUNTING 1st 2nd 1st 2nd 1st 2nd 60 Hz 1st 2nd 1st 2nd 1st 2nd 1 314 2 315 312 625 4 267 5 268 265 3 ...260 1 0 0 0 0 0 1 0 1 0... 0 0 0 0 0 0 0 0 0 262 1 0 0 0 0 0 1 1 0 ...310 1 0 0 1 1 0 1 1 1 0... 0 0 0 0 0 0 0 0 0 DECIMAL VALUE 312 MSB 17H[0] VSTA8 50 Hz 1 VSTA7 0 VSTA6 0 CONTROL BITS 7 TO 0 VSTA5 1 VSTA4 1 VSTA3 1 VSTA2 0 VSTA1 0 VSTA0 0
FIELD
SAA7108AE; SAA7109AE
Product specification
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18.2.2.23 Subaddress 16H
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HD-CODEC
Table 176 VGATE stop; 17H[1] and 16H[7:0] Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; see Figs 30 and 31. FRAME LINE COUNTING 1st 2nd 1st 2nd 1st 2nd 60 Hz 1st 2nd 1st 2nd 1st 2nd 1 314 2 315 312 625 4 267 5 268 265 3 ...260 1 0 0 0 0 0 1 0 1 0... 0 0 0 0 0 0 0 0 0 262 1 0 0 0 0 0 1 1 0 ...310 1 0 0 1 1 0 1 1 1 0... 0 0 0 0 0 0 0 0 0 DECIMAL VALUE 312 MSB 17H[1] VSTO8 50 Hz 1 VSTO7 0 VSTO6 0 VSTO5 1 CONTROL BITS 7 TO 0 VSTO4 1 VSTO3 1 VSTO2 0 VSTO1 0 VSTO0 0
FIELD
SAA7108AE; SAA7109AE
Product specification
Philips Semiconductors
Product specification
HD-CODEC
18.2.2.24 Subaddress 17H
Table 177 Miscellaneous/VGATE MSBs; 17H[7:6] and 17H[2:0] BIT 7 6 2 1 0 DESCRIPTION LLC output enable LLC2 output enable alternative VGATE position MSB VGATE stop MSB VGATE start SYMBOL LLCE LLC2E VGPS VSTO8 VSTA8 VALUE 0 1 0 1 0 1 enable 3-state enable 3-state
SAA7108AE; SAA7109AE
FUNCTION
VGATE position according to Tables 175 and 176 VGATE occurs one line earlier during field 2 see Table 176 see Table 175
18.2.2.25 Subaddress 18H
Table 178 Raw data gain control; RAWG[7:0] 18H[7:0]; see Fig.27 CONTROL BITS 7 TO 0 GAIN RAWG7 255 (double amplitude) 128 (nominal level) 0 (off) 0 0 0 RAWG6 1 1 0 RAWG5 1 0 0 RAWG4 1 0 0 RAWG3 1 0 0 RAWG2 1 0 0 RAWG1 1 0 0 RAWG0 1 0 0
18.2.2.26 Subaddress 19H
Table 179 Raw data offset control; RAWO[7:0] 19H[7:0]; see Fig.27 CONTROL BITS 7 TO 0 OFFSET RAWO7 -128 LSB 0 LSB +128 LSB 0 1 1 RAWO6 0 0 1 RAWO5 0 0 1 RAWO4 0 0 1 RAWO3 0 0 1 RAWO2 0 0 1 RAWO1 0 0 1 RAWO0 0 0 1
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Philips Semiconductors
Product specification
HD-CODEC
18.2.2.27 Subaddress 1FH
Table 180 Status byte video decoder; 1FH[7:0]; read only register BIT 7 6 DESCRIPTION status bit for interlace detection status bit for horizontal and vertical loop status bit for locked horizontal frequency 5 4 3 2 1 identification bit for detected field frequency gain value for active luminance channel is limited; maximum (top) gain value for active luminance channel is limited; minimum (bottom) white peak loop is activated copy protected source detected according to Macrovision version up to 7.01 slow time constant active in WIPA mode 0 ready for capture (all internal loops locked) colour signal in accordance with selected standard has been detected 18.2.3 PROGRAMMING REGISTER AUDIO CLOCK GENERATION I2C-BUS CONTROL BIT INTL HLVLN HLCK FIDT GLIMT GLIMB WIPA COPRO SLTCA RDCAP CODE
SAA7108AE; SAA7109AE
OLDSB 14H[2] - 0 1 - - - - 0 1 0 1
VALUE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
FUNCTION non-interlaced interlaced both loops locked unlocked locked unlocked 50 Hz 60 Hz not active active not active active not active active not active active not active active not active active not active active
See equations in Section 9.6 and examples in Tables 35 and 36.
18.2.3.1
Subaddresses 30H to 32H
Table 181 Audio master clock (AMCLK) cycles per field SUBADDRESS 30H 31H 32H ACPF7 ACPF15 - ACPF6 ACPF14 - ACPF5 ACPF13 - CONTROL BITS 7 TO 0 ACPF4 ACPF12 - ACPF3 ACPF11 - ACPF2 ACPF10 - ACPF1 ACPF9 ACPF17 ACPF0 ACPF8 ACPF16
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Philips Semiconductors
Product specification
HD-CODEC
18.2.3.2 Subaddresses 34H to 36H
SAA7108AE; SAA7109AE
Table 182 Audio master clock (AMCLK) nominal increment SUBADDRESS 34H 35H 36H ACNI7 ACNI15 - ACNI ACNI14 - ACNI5 ACNI13 ACNI21 CONTROL BITS 7 TO 0 ACNI4 ACNI12 ACNI20 ACNI3 ACNI11 ACNI19 ACNI2 ACNI10 ACNI18 ACNI1 ACNI9 ACNI17 ACNI0 ACNI8 ACNI16
18.2.3.3
Subaddress 38H
Table 183 Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK) SUBADDRESS 38H - - SDIV5 CONTROL BITS 7 TO 0 SDIV4 SDIV3 SDIV2 SDIV1 SDIV0
18.2.3.4
Subaddress 39H
Table 184 Clock ratio serial bit clock (ASCLK) to channel select clock (ALRCLK) SUBADDRESS 39H - - LRDIV5 CONTROL BITS 7 TO 0 LRDIV4 LRDIV3 LRDIV2 LRDIV1 LRDIV0
18.2.3.5
Subaddress 3AH
Table 185 Audio clock control; 3AH[3:0] BIT 3 2 DESCRIPTION audio PLL modes audio master clock vertical reference ALRCLK phase ASCLK phase SYMBOL APLL AMVR VALUE 0 1 0 1 LRPH SCPH 0 1 0 0 1 18.2.4 PROGRAMMING REGISTER VBI DATA SLICER FUNCTION PLL active, AMCLK is field-locked PLL open, AMCLK is free-running vertical reference pulse is taken from internal decoder vertical reference is taken from XRV input (expansion port) ALRCLK edges triggered by falling edges of ASCLK ALRCLK edges triggered by rising edges of ASCLK ASCLK edges triggered by falling edges of AMCLK ASCLK edges triggered by rising edges of AMCLK
1
18.2.4.1
Subaddress 40H
Table 186 Slicer control 1; 40H[6:4] BIT 6 DESCRIPTION Hamming check SYMBOL HAM_N VALUE 0 1 5 4 framing code error amplitude searching FCE HUNT_N 0 1 0 1 2004 Jun 29 164 FUNCTION Hamming check for 2 bytes after framing code, dependent on data type (default) no Hamming check one framing code error allowed no framing code errors allowed amplitude searching active (default) amplitude searching stopped
Philips Semiconductors
Product specification
HD-CODEC
18.2.4.2 Subaddresses 41H to 57H
SAA7108AE; SAA7109AE
Table 187 Line control register; LCR2 to LCR24 (41H to 57H); see Sections 9.2 and 9.4 BITS 7 TO 4 (41H TO 57H) NAME DESCRIPTION FRAMING CODE DT[3:0] 62H[3:0] (FIELD 1) WST625 CC625 VPS WSS WST525 CC525 Test line Intercast VITC625 VITC525 Reserved NABTS Japtext JFS teletext EuroWST, CCST European Closed Caption video programming service wide screen signalling bits US teletext (WST) US Closed Caption (line 21) video component signal, VBI region raw data VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved US NABTS MOJI (Japanese) Japanese format switch (L20/22) 27H 001 9951H 1E3C1FH 27H 001 - - programmable programmable programmable - - programmable (A7H) programmable - 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DT[3:0] 62H[3:0] (FIELD 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 BITS 3 TO 0 (41H TO 57H)
General text teletext
Active video video component signal, active video region (default)
18.2.4.3
Subaddress 58H
Table 188 Programmable framing code; slicer set 58H[7:0]; see Tables 28 and 187 FRAMING CODE FOR PROGRAMMABLE DATA TYPES Default value CONTROL BITS 7 TO 0 FC[7:0] = 40H
18.2.4.4
Subaddress 59H
Table 189 Horizontal offset for slicer; slicer set 59H and 5BH HORIZONTAL OFFSET Recommended value CONTROL BITS 5BH[2:0] HOFF[10:8] = 3H CONTROL BITS 59H[7:0] HOFF[7:0] = 47H
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Product specification
HD-CODEC
18.2.4.5 Subaddress 5AH
SAA7108AE; SAA7109AE
Table 190 Vertical offset for slicer; slicer set 5AH and 5BH VERTICAL OFFSET Minimum value 0 Maximum value 312 Value for 50 Hz 625 lines input Value for 60 Hz 525 lines input CONTROL BIT 5BH[4] VOFF8 0 1 0 0 CONTROL BITS 5AH[7:0] VOFF[7:0] 00H 38H 03H 06H
18.2.4.6
Subaddress 5BH
Table 191 Field offset, and MSBs for horizontal and vertical offsets; slicer set 5BH[7:6] See Sections 18.2.4.4 and 18.2.4.5 for HOFF[10:8] 5BH[2:0] and VOFF8[5BH[4]]. BIT 7 DESCRIPTION SYMBOL field offset FOFF VALUE 0 1 6 recode RECODE 0 1 FUNCTION no modification of internal field indicator (default for 50 Hz 625 lines input sources) invert field indicator (default for 60 Hz 525 lines input sources) let data unchanged (default) convert 00H and FFH data bytes into 03H and FCH
18.2.4.7
Subaddress 5DH
Table 192 Header and data identification (DID; ITU 656) code control; slicer set 5DH[7:0] BIT 7 DESCRIPTION field ID and V-blank selection for text output (F and V reference selection) default; DID[5:0] = 00H special cases of DID programming SYMBOL FVREF VALUE 0 1 FUNCTION F and V output of slicer is LCR table dependent F and V output is taken from decoder real time signals EVEN_ITU and VBLNK_ITU ANC header framing; see Fig.39 and Table 34 DID[5:0] = 3EH SAV/EAV framing, with FVREF = 1 DID[5:0] = 3FH SAV/EAV framing, with FVREF = 0
5 to 0
DID[5:0]
00 0000 11 1110 11 1111
18.2.4.8
Subaddress 5EH
Table 193 Sliced data identification (SDID) code; slicer set 5EH[5:0] BIT 5 to 0 DESCRIPTION SDID codes SYMBOL SDID[5:0] VALUE 00H default FUNCTION
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Product specification
HD-CODEC
18.2.4.9 Subaddress 60H
SAA7108AE; SAA7109AE
Table 194 Slicer status byte 0; 60H[6:2]; read only register BIT 6 5 4 3 2 DESCRIPTION framing code valid framing code valid VPS valid PALplus valid Closed Caption valid SYMBOL FC8V FC7V VPSV PPV CCV VALUE 0 1 0 1 0 1 0 1 0 1 FUNCTION no framing code (0 error) in the last frame detected framing code with 0 error detected no framing code (1 error) in the last frame detected framing code with 1 error detected no VPS in the last frame VPS detected no PALplus in the last frame PALplus detected no Closed Caption in the last frame Closed Caption detected
18.2.4.10 Subaddresses 61H and 62H
Table 195 Slicer status byte 1; 61H[5:0] and slicer status byte 2; 62H[7:0]; read only registers SUBADDRESS 61H 62H BIT 5 4 to 0 7 to 4 3 to 0 18.2.5 SYMBOL F21_N LN[8:4] LN[3:0] DT[3:0] data type; according to Table 28 line number DESCRIPTION field ID as seen by the VBI slicer; for field 1: bit 5 = 0
PROGRAMMING REGISTER INTERFACES AND SCALER PART
18.2.5.1
Subaddress 80H
Table 196 Global control 1; global set 80H[6:4] SWRST moved to subaddress 88H[5]; note 1. CONTROL BITS 6 TO 4 TASK ENABLE CONTROL SMOD Task of register set A is disabled Task of register set A is enabled Task of register set B is disabled Task of register set B is enabled The scaler window defines the F and V timing of the scaler output VBI data slicer defines the F and V timing of the scaler output Note 1. X = don't care. X X X X 0 1 TEB X X 0 1 X X TEA 0 1 X X X X
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Product specification
HD-CODEC
Table 197 Global control 1; global set 80H[3:0]; note 1
SAA7108AE; SAA7109AE
CONTROL BITS 3 TO 0 I PORT AND SCALER BACK-END CLOCK SELECTION ICKS3 ICLK output and back-end clock is line-locked clock LLC from decoder ICLK output and back-end clock is XCLK from X port ICLK output is LLC and back-end clock is LLC2 clock Back-end clock is the ICLK input IDQ pin carries the data qualifier IDQ pin carries a gated back-end clock (IDQ AND CLK) IDQ generation only for valid data IDQ qualifies valid data inside the scaling region and all data outside the scaling region Notes 1. Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1. 2. X = don't care. X X X X X X 0 1 ICKS2 X X X(2) X 0 1 X X ICKS1 0 0 1 1 X X X X ICKS0 0 1 0 1 X X X X
18.2.5.2
Subaddresses 83H to 87H
Table 198 X port I/O enable and output clock phase control; global set 83H[5:4] CONTROL BITS 5 AND 4 OUTPUT CLOCK PHASE CONTROL XPCK1 XCLK default output phase, recommended value XCLK output inverted XCLK phase shifted by about 3 ns XCLK output inverted and shifted by about 3 ns Table 199 X port I/O enable and output clock phase control; global set 83H[2:0] CONTROL BITS 2 TO 0 X PORT I/O ENABLE XRQT X port output is disabled by software X port output is enabled by software X port output is enabled by pin XTRI at logic 0 X port output is enabled by pin XTRI at logic 1 XRDY output signal is A/B task flag from event handler (A = 1) XRDY output signal is ready signal from scaler path (XRDY = 1 means SAA7108AE; SAA7109AE is ready to receive data) Note 1. X = don't care X(1) X X X 0 1 XPE1 0 0 1 1 X X XPE0 0 1 0 1 X X 0 0 1 1 XPCK0 0 1 0 1
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Philips Semiconductors
Product specification
HD-CODEC
Table 200 I port signal definitions; global set 84H[7:6] and 86H[5]
SAA7108AE; SAA7109AE
CONTROL BITS I PORT SIGNAL DEFINITIONS 86H[5] IDG02 IGP0 is output field ID, as defined by OFIDC[90H[6]] IGP0 is A/B task flag, as defined by CONLH[90H[7]] IGP0 is sliced data flag, framing the sliced VBI data at the I port IGP0 is set to logic 0 (default polarity) IGP0 is the output FIFO almost filled flag IGP0 is the output FIFO overflow flag IGP0 is the output FIFO almost full flag, level to be programmed in subaddress 86H IGP0 is the output FIFO almost empty flag, level to be programmed in subaddress 86H Table 201 I port signal definitions; global set 84H[5:4] and 86H[4] CONTROL BITS I PORT SIGNAL DEFINITIONS 86H[4] IDG12 IGP1 is output field ID, as defined by OFIDC[90H[6]] IGP1 is A/B task flag, as defined by CONLH[90H[7]] IGP1 is sliced data flag, framing the sliced VBI data at the I port IGP1 is set to logic 0 (default polarity) IGP1 is the output FIFO almost filled flag IGP1 is the output FIFO overflow flag IGP1 is the output FIFO almost full flag, level to be programmed in subaddress 86H IGP1 is the output FIFO almost empty flag, level to be programmed in subaddress 86H Table 202 I port output signal definitions; global set 84H[3:0]; note 1 CONTROL BITS 3 TO 0 I PORT OUTPUT SIGNAL DEFINITIONS IDV1 IGPH is a H gate signal, framing the scaler output IGPH is an extended H gate (framing H gate during scaler output and scaler input H reference outside the scaler window) IGPH is a horizontal trigger pulse, on active going edge of H gate IGPH is a horizontal trigger pulse, on active going edge of extended H gate IGPV is a V gate signal, framing scaled output lines IGPV is the V reference signal from scaler input IGPV is a vertical trigger pulse, derived from V gate IGPV is a vertical trigger pulse derived from input V reference Note 1. X = don't care. X X X X 0 0 1 1 IDV0 X X X X 0 1 0 1 IDH1 0 0 1 1 X X X X IDH0 0 1 0 1 X X X X 0 0 0 0 1 1 1 1 84H[5:4] IDG11 0 0 1 1 0 0 1 1 IDG10 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 84H[7:6] IDG01 0 0 1 1 0 0 1 1 IDG00 0 1 0 1 0 1 0 1
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Philips Semiconductors
Product specification
HD-CODEC
Table 203 X port signal definitions text slicer; global set 85H[7:5]; note 1
SAA7108AE; SAA7109AE
CONTROL BITS 7 TO 5 X PORT SIGNAL DEFINITIONS TEXT SLICER ISWP1 Video data limited to range 1 to 254 Video data limited to range 8 to 247 Dword byte swap, influences serial output timing D0 D1 D2 D3 FF 00 00 SAV CB0 Y0 CR0 Y1 D1 D0 D3 D2 00 FF SAV 00 Y0 CB0 Y1 CR0 D2 D3 D0 D1 00 SAV FF 00 CR0 Y1 CB0 Y0 D3 D2 D1 D0 SAV 00 00 FF Y1 CR0 Y0 CB0 Note 1. X = don't care. Table 204 I port reference signal polarities; global set 85H[4:0]; note 1 CONTROL BITS 4 TO 0 I PORT REFERENCE SIGNAL POLARITIES IG0P IDQ at default polarity (1 = active) IDQ is inverted IGPH at default polarity (1 = active) IGPH is inverted IGPV at default polarity (1 = active) IGPV is inverted IGP1 at default polarity IGP1 is inverted IGP0 at default polarity IGP0 is inverted Note 1. X = don't care. X X X X X X X X 0 1 IG1P X X X X X X 0 1 X X IRVP X X X X 0 1 X X X X IRHP X X 0 1 X X X X X X IDQP 0 1 X X X X X X X X X X 0 0 1 1 ISWP0 X X 0 1 0 1 ILLV 0 1 X X X X
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Philips Semiconductors
Product specification
HD-CODEC
Table 205 I port FIFO flag control and arbitration; global set 86H[7:4]; note 1
SAA7108AE; SAA7109AE
CONTROL BITS 7 TO 4 FUNCTION VITX1 See subaddress 84H: IDG11 and IDG10 See subaddress 84H: IDG01 and IDG00 I port signal definitions I port data output inhibited Only video data are transferred Only text data are transferred (no EAV, SAV will occur) Text and video data are transferred, text has priority Note 1. X = don't care. Table 206 I port FIFO flag control and arbitration; global set 86H[3:0]; note 1 CONTROL BITS 3 TO 0 I PORT FIFO FLAG CONTROL AND ARBITRATION FFL1 FAE FIFO flag almost empty level <16 Dwords <8 Dwords <4 Dwords 0 Dwords FAF FIFO flag almost full level 16 Dwords 24 Dwords 28 Dwords 32 Dwords Note 1. X = don't care. 0 0 1 1 0 1 0 1 X X X X X X X X X X X X X X X X 0 0 1 1 0 1 0 1 FFL0 FEL1 FEL0 0 0 1 1 0 1 0 1 X X X X X X X X X X X X VITX0 X X X X IDG02 X X 0 1 IDG12 0 1 X X
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Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
Table 207 I port I/O enable, output clock and gated clock phase control; global set 87H[7:4]; note 1 CONTROL BITS 7 TO 4 OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL ICLK default output phase ICLK phase shifted by 12 clock cycle recommended for ICKS1 = 1 and ICKS0 = 0 (subaddress 80H) ICLK phase shifted by about 3 ns ICLK phase shifted by 2 clock cycle + approximately 3 ns alternatively to setting `01' IDQ = gated clock default output phase IDQ = gated clock phase shifted by for gated clock output
1 2 1
IPCK3(2) X X X X 0 0 1 1
IPCK2(2) X X X X 0 1 0 1
IPCK1 0 0 1 1 X X X X
IPCK0 0 1 0 1 X X X X
clock cycle recommended
IDQ = gated clock phase shifted by approximately 3 ns IDQ = gated clock phase shifted by 12 clock cycle + approximately 3 ns alternatively to setting `01' Notes 1. X = don't care.
2. IPCK3 and IPCK2 only affects the gated clock (subaddress 80H, bit ICKS2 = 1). Table 208 I port I/O enable, output clock and gated clock phase control; global set 87H[1:0] CONTROL BITS 1 AND 0 I PORT I/O ENABLE IPE1 I port output is disabled by software I port output is enabled by software I port output is enabled by pin ITRI at logic 0 I port output is enabled by pin ITRI at logic 1 0 0 1 1 IPE0 0 1 0 1
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Philips Semiconductors
Product specification
HD-CODEC
18.2.5.3 Subaddress 88H
SAA7108AE; SAA7109AE
Table 209 Power save control; global set 88H[7:4]; note 1 CONTROL BITS 7 TO 4 POWER SAVE CONTROL CH4EN DPROG = 0 after reset DPROG = 1 can be used to assign that the device has been programmed; this bit can be monitored in the scalers status byte, bit PRDON; if DPROG was set to logic 1 and PRDON status bit shows a logic 0, a power-up or start-up fail has occurred Scaler path is reset to its idle state, software reset Scaler is switched back to operation AD1x analog channel is in Power-down mode AD1x analog channel is active AD2x analog channel is in Power-down mode AD2x analog channel is active Notes 1. X = don't care. 2. Bit SWRST is now located here. Table 210 Power save control; global set 88H[3] and 88H[1:0]; note 1 CONTROL BITS 3, 1 AND 0 POWER SAVE CONTROL SLM3 Decoder and VBI slicer are in operational mode Decoder and VBI slicer are in Power-down mode; scaler only operates, if scaler input and ICLK source is the X port (refer to subaddresses 80H and 91H/C1H) Scaler is in operational mode Scaler is in Power-down mode; scaler in power-down stops I port output Audio clock generation active Audio clock generation in power-down and output disabled Note 1. X = don't care. X X X X 0 1 SLM1 X X 0 1 X X SLM0 0 1 X X X X X X CH2EN X X SWRST(2) X X DPROG 0 1
X X X X 0 1
X X 0 1 X X
0 1 X X X X
X X X X X X
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Philips Semiconductors
Product specification
HD-CODEC
18.2.5.4 Subaddress 8FH
SAA7108AE; SAA7109AE
Table 211 Status information scaler part; 8FH[7:0]; read only register BIT 7 6 5 4 3 2 I2C-BUS STATUS BIT XTRI ITRI FFIL FFOV PRDON ERROF FUNCTION(1) status on input pin XTRI, if not used for 3-state control, usable as hardware flag for software use status on input pin ITRI, if not used for 3-state control, usable as hardware flag for software use status of the internal `FIFO almost filled' flag status of the internal `FIFO overflow' flag copy of bit DPROG, can be used to detect power-up and start-up fails error flag of scalers output formatter, normally set, if the output processing needs to be interrupted, due to input/output data rate conflicts, e.g. if output data rate is much too low and all internal FIFO capacity used status of the field sequence ID at the scalers input status of the field sequence ID at the scalers output, scaler processing dependent
1 0 Note
FIDSCI FIDSCO
1. Status information is unsynchronized and shows the actual status at the time of I2C-bus read.
18.2.5.5
Subaddresses 90H and C0H
Table 212 Task handing control; register set A [90H[7:6]] and B [C0H[7:6]]; note 1 CONTROL BITS 7 AND 6 EVENT HANDLER CONTROL CONLH Output field ID is field ID from scaler input Output field ID is task status flag, which changes every time an selected task is activated (not synchronized to input field ID) Scaler SAV/EAV byte bit 7 and task flag = 1, default Scaler SAV/EAV byte bit 7 and task flag = 0 Note 1. X = don't care. Table 213 Task handling control; register set A [90H[5:3]] and B [C0H[5:3]] CONTROL BITS 5 TO 3 EVENT HANDLER CONTROL FSKP2 Active task is carried out directly 1 field is skipped before active task is carried out ... fields are skipped before active task is carried out 6 fields are skipped before active task is carried out 7 fields are skipped before active task is carried out 0 0 ... 1 1 FSKP1 0 0 ... 1 1 FSKP0 0 1 ... 0 1 X X 0 1 OFIDC 0 1 X X
2004 Jun 29
174
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
Table 214 Task handling control; register set A [90H[2:0]] and B [C0H[2:0]]; note 1 CONTROL BITS 2 TO 0 EVENT HANDLER CONTROL RPTSK Event handler triggers immediately after finishing a task Event handler triggers with next V-sync Event handler triggers with field ID = 0 Event handler triggers with field ID = 1 If active task is finished, handling is taken over by the next task Active task is repeated once, before handling is taken over by the next task Note 1. X = don't care. X X X X 0 1 STRC1 0 0 1 1 X X STRC0 0 1 0 1 X X
18.2.5.6
Subaddresses 91H to 93H
Table 215 X port formats and configuration; register set A [91H[7:3]] and B [C1H[7:3]]; note 1 SCALER INPUT FORMAT AND CONFIGURATION SOURCE SELECTION Only if XRQT[83H[2]] = 1: scaler input source reacts on SAA7108AE; SAA7109AE request Scaler input source is a continuous data stream, which cannot be interrupted (must be logic 1 if SAA7108AE; SAA7109AE decoder part is source of scaler or XRQT[83H[2]] = 0) Scaler input source is data from decoder, data type is provided according to Table 28 Scaler input source is Y-CB-CR data from X port Scaler input source is raw digital CVBS from selected analog channel, for backward compatibility only, further use is not recommended Scaler input source is raw digital CVBS (or 16-bit Y + CB-CR, if no 16-bit output are active) from X port SAV/EAV code bits 6 and 5 (F and V) may change between SAV and EAV SAV/EAV code bits 6 and 5 (F and V) are synchronized to scalers output line start SAV/EAV code bit 5 (V) and V gate on pin IGPV as generated by the internal processing; see Fig.45 SAV/EAV code bit 5 (V) and V gate are inverted Note 1. X = don't care. CONTROL BITS 7 TO 3 CONLV X X HLDFV X X SCSRC1 SCSRC0 X X X X SCRQE 0 1
X X X
X X X
0 0 1
0 1 0
X X X
X X X 0 1
X 0 1 X X
1 X X X X
1 X X X X
X X X X X
2004 Jun 29
175
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
Table 216 X port formats and configuration; register set A [91H[2:0]] and B [C1H[2:0]]; note 1 SCALER INPUT FORMAT AND CONFIGURATION FORMAT CONTROL Input is Y-CB-CR 4 : 2 : 2 like sampling scheme Input is Y-CB-CR 4 : 1 : 1 like sampling scheme Chroma is provided every line, default Chroma is provided every 2nd line Chroma is provided every 3rd line Chroma is provided every 4th line Notes 1. X = don't care. 2. FSC2 and FSC1 only to be used, if X port input source don't provide chroma information for every input line. X port input stream must contain dummy chroma bytes. Table 217 X port input reference signal definitions; register set A [92H[7:4]] and B [C2H[7:4]]; note 1 CONTROL BITS 7 TO 4 X PORT INPUT REFERENCE SIGNAL DEFINITIONS XFDV Rising edge of XRV input and decoder V123 is vertical reference Falling edge of XRV input and decoder V123 is vertical reference XRV is a V-sync or V gate signal XRV is a frame sync, V pulses are generated internally on both edges of FS input X port field ID is state of XRH at reference edge on XRV (defined by XFDV) Field ID (decoder and X port field ID) is inverted Reference edge for field detection is falling edge of XRV Reference edge for field detection is rising edge of XRV Note 1. X = don't care. X X X X X X 0 1 XFDH X X X X 0 1 X X XDV1 X X 0 1 X X X X XDV0 0 1 X X X X X X CONTROL BITS 2 TO 0 FSC2(2) X X 0 0 1 1 FSC1(2) X X 0 1 0 1 FSC0 0 1 X X X X
2004 Jun 29
176
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
Table 218 X port input reference signal definitions; register set A [92H[3:0]] and B [C2H[3:0]]; note 1 CONTROL BITS 3 TO 0 X PORT INPUT REFERENCE SIGNAL DEFINITIONS XCODE XCLK input clock and XDQ input qualifier are needed Data rate is defined by XCLK only, no XDQ signal used Data are qualified at XDQ input at logic 1 Data are qualified at XDQ input at logic 0 Rising edge of XRH input is horizontal reference Falling edge of XRH input is horizontal reference Reference signals are taken from XRH and XRV Reference signals are decoded from EAV and SAV Note 1. X = don't care. Table 219 I port output format and configuration; register set A [93H[7:5]] and B [C3H[7:5]]; note 1 CONTROL BITS 7 TO 5 I PORT OUTPUT FORMATS AND CONFIGURATION ICODE All lines will be output Skip the number of leading Y only lines, as defined by FOI1 and FOI0 Dwords are transferred byte wise, see subaddress 85H bits ISWP1 and ISWP0 Dwords are transferred 16-bit word wise via IPD and HPD, see subaddress 85H bits ISWP1 and ISWP0 No ITU 656 like SAV/EAV codes are available ITU 656 like SAV/EAV codes are inserted in the output data stream, framed by a qualifier Note 1. X = don't care. X X X X 0 1 I8_16 X X 0 1 X X FYSK 0 1 X X X X X X X X X X 0 1 XDH X X X X 0 1 X X XDQ X X 0 1 X X X X XCKS 0 1 X X X X X X
2004 Jun 29
177
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
Table 220 I port output format and configuration; register set A [93H[4:0]] and B [C3H[4:0]]; note 1 CONTROL BITS 4 TO 0 I PORT OUTPUT FORMATS AND CONFIGURATION FOI1 4 : 2 : 2 Dword formatting 4 : 1 : 1 Dword formatting 4 : 2 : 0, only every 2nd line Y + CB-CR output, in between Y only output 4 : 1 : 0, only every 4th line Y + CB-CR output, in between Y only output Y only Not defined Not defined Not defined No leading Y only line, before 1st Y + CB-CR line is output 1 leading Y only line, before 1st Y + CB-CR line is output 2 leading Y only lines, before 1st Y + CB-CR line is output 3 leading Y only lines, before 1st Y + CB-CR line is output Note 1. X = don't care. X X X X X X X X 0 0 1 1 FOI0 X X X X X X X X 0 1 0 1 FSI2 0 0 0 0 1 1 1 1 X X X X FSI1 0 0 1 1 0 0 1 1 X X X X FSI0 0 1 0 1 0 1 0 1 X X X X
18.2.5.7
Subaddresses 94H to 9BH
Table 221 Horizontal input window start; register set A [94H[7:0]; 95H[3:0]] and B [C4H[7:0]; C5H[3:0]] HORIZONTAL INPUT ACQUISITION WINDOW DEFINITION OFFSET IN X (HORIZONTAL) DIRECTION(1) A minimum of 2 should be kept, due to a line counting mismatch Odd offsets are changing the CB-CR sequence in the output stream to CR-CB sequence Maximum possible pixel offset = 4095 Note 1. Reference for counting are luminance samples. CONTROL BITS A [95H[3:0]] B [C5H[3:0]] A [94H[7:0]] B [C4H[7:0]]
XO11 XO10 XO9 XO8 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
1
1
1
1
1
1
1
1
1
1
1
1
2004 Jun 29
178
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
Table 222 Horizontal input window length; register set A [96H[7:0]; 97H[3:0]] and B [C6H[7:0]; C7H[3:0]] HORIZONTAL INPUT ACQUISITION WINDOW DEFINITION INPUT WINDOW LENGTH IN X (HORIZONTAL) DIRECTION(1) No output Odd lengths are allowed, but will be rounded up to even lengths Maximum possible number of input pixels = 4095 Note 1. Reference for counting are luminance samples. Table 223 Vertical input window start; register set A [98H[7:0]; 99H[3:0]] and B [C8H[7:0]; C9H[3:0]] CONTROL BITS VERTICAL INPUT ACQUISITION WINDOW DEFINITION OFFSET IN Y (VERTICAL) DIRECTION(1) Line offset = 0 Line offset = 1 Maximum line offset = 4095 Note 1. For trigger condition: STRC[1:0] 90H[1:0] = 00; YO + YS > (number of input lines per field - 2), will result in field dropping. Other trigger conditions: YO > (number of input lines per field - 2), will result in field dropping. Table 224 Vertical input window length; register set A [9AH[7:0]; 9BH[3:0]] and B [CAH[7:0]; CBH[3:0]] VERTICAL INPUT ACQUISITION WINDOW DEFINITION INPUT WINDOW LENGTH IN Y (VERTICAL) DIRECTION(1) No input lines 1 input line Maximum possible number of input lines = 4095 Note 1. For trigger condition: STRC[1:0] 90H[1:0] = 00; YO + YS > (number of input lines per field - 2), will result in field dropping. Other trigger conditions: YS > (number of input lines per field - 2), will result in field dropping. CONTROL BITS A [9BH[3:0]] B [CBH[3:0]] A [9AH[7:0]] B [CAH[7:0]] 0 0 1 A [99H[3:0]] B [C9H[3:0]] A [98H[7:0]] B [C8H[7:0]] CONTROL BITS A [97H[3:0]] B [C7H[3:0]] A [96H[7:0]] B [C6H[7:0]]
XS11 XS10 XS9 XS8 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1
YO11 YO10 YO9 YO8 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1
YS11 YS10 YS9 YS8 YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1
2004 Jun 29
179
Philips Semiconductors
Product specification
HD-CODEC
18.2.5.8 Subaddresses 9CH to 9FH
SAA7108AE; SAA7109AE
Table 225 Horizontal output window length; register set A [9CH[7:0]; 9DH[3:0]] and B [CCH[7:0]; CDH[3:0]] HORIZONTAL OUTPUT ACQUISITION WINDOW DEFINITION NUMBER OF DESIRED OUTPUT PIXEL IN X (HORIZONTAL) DIRECTION(1) No output Odd lengths are allowed, but will be filled up to even lengths Maximum possible number of input pixels = 4095; note 2 Notes 1. Reference for counting are luminance samples. 2. If the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated. Table 226 Vertical output window length; register set A [9EH[7:0]; 9FH[3:0]] and B [CEH[7:0]; CFH[3:0]] VERTICAL OUTPUT ACQUISITION WINDOW DEFINITION NUMBER OF DESIRED OUTPUT LINES IN Y (VERTICAL) DIRECTION No output 1 pixel Maximum possible number of output lines = 4095; note 1 Note 1. If the desired output length is greater than the number of scaled output lines, the processing is cut. CONTROL BITS A [9FH[3:0]] B [CFH[3:0]] A [9EH[7:0]] B [CEH[7:0]] CONTROL BITS A [9DH[3:0]] B [CDH[3:0]] A [9CH[7:0]] B [CCH[7:0]]
XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1
YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1
18.2.5.9
Subaddresses A0H to A2H
Table 227 Horizontal prescaling; register set A [A0H[5:0]] and B [D0H[5:0]] CONTROL BITS 5 TO 0 HORIZONTAL INTEGER PRESCALING RATIO (XPSC) XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0 Not allowed Downscale = 1 Downscale = 12 ... Downscale =
1 63
0 0 0 ... 1
0 0 0 ... 1
0 0 0 ... 1
0 0 0 ... 1
0 0 1 ... 1
0 1 0 ... 1
2004 Jun 29
180
Philips Semiconductors
Product specification
HD-CODEC
Table 228 Accumulation length; register set A [A1H[5:0]] and B [D1H[5:0]] HORIZONTAL PRESCALER ACCUMULATION SEQUENCE LENGTH (XACL) Accumulation length = 1 Accumulation length = 2 ... Accumulation length = 64
SAA7108AE; SAA7109AE
CONTROL BITS 5 TO 0 XACL5 XACL4 XACL3 XACL2 XACL1 XACL0 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 1 ... 1
Table 229 Prescaler DC gain and FIR prefilter control; register set A [A2H[7:4]] and B [D2H[7:4]]; note 1 CONTROL BITS 7 TO 4 FIR PREFILTER CONTROL PFUV1 Luminance FIR filter bypassed H_y(z) = H_y(z) = H_y(z) =
1 4 1 8 1 8 1
PFUV0 X X X X 0 1 0 1
PFY1 0 0 1 1 X X X X
PFY0 0 1 0 1 X X X X
X X X X 0 0 1 1
(1 2 1) (-1 1 1.75 4.5 1.75 1 -1) (1 2 2 2 1) (1 2 1)
Chrominance FIR filter bypassed H_uv(z) =
4
H_uv(z) = 132 (3 8 10 8 3) H_uv(z) = 18 (1 2 2 2 1) Note 1. X = don't care.
Table 230 Prescaler DC gain and FIR prefilter control; register set A [A2H[3:0]] and B [D2H[3:0]]; note 1 CONTROL BITS 3 TO 0 PRESCALER DC GAIN XC2_1 Prescaler output is renormalized by gain factor = 1 Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = Prescaler output is renormalized by gain factor = Weighting of all accumulated samples is factor 1; e.g. XACL = 4 sequence 1 + 1 + 1 + 1 + 1 Weighting of samples inside sequence is factor 2; e.g. XACL = 4 sequence 1 + 2 + 2 + 2 + 1 Note 1. X = don't care.
1 1 1 1 1 2
XDCG2 0 0 0 0 1 1 1 1 X X
XDCG1 0 0 1 1 0 0 1 1 X X
XDCG0 0 1 0 1 0 1 0 1 X X
X X X X X X X X 0 1
Prescaler output is renormalized by gain factor = 14
8 16 32
Prescaler output is renormalized by gain factor = 164
128
2004 Jun 29
181
Philips Semiconductors
Product specification
HD-CODEC
18.2.5.10 Subaddresses A4H to A6H
SAA7108AE; SAA7109AE
Table 231 Luminance brightness control; register set A [A4H[7:0]] and B [D4H[7:0]] LUMINANCE BRIGHTNESS CONTROL Value = 0 Nominal value = 128 Value = 255 CONTROL BITS 7 TO 0 BRIG7 0 1 1 BRIG6 0 0 1 BRIG5 0 0 1 BRIG4 0 0 1 BRIG3 0 0 1 BRIG2 0 0 1 BRIG1 0 0 1 BRIG0 0 0 1
Table 232 Luminance contrast control; register set A [A5H[7:0]] and B [D5H[7:0]] LUMINANCE CONTRAST CONTROL Gain = 0 Gain = Gain =
1 64
CONTROL BITS 7 TO 0 CONT7 0 0 0 0 CONT6 0 0 1 1 CONT5 0 0 0 1 CONT4 0 0 0 1 CONT3 0 0 0 1 CONT2 0 0 0 1 CONT1 0 0 0 1 CONT0 0 1 0 1
Nominal gain = 64
127 64
Table 233 Chrominance saturation control; register set A [A6H[7:0]] and B [D6H[7:0]] CHROMINANCE SATURATION CONTROL Gain = 0 Gain = 164 Nominal gain = 64 Gain =
127 64
CONTROL BITS 7 TO 0 SATN7 0 0 0 0 SATN6 0 0 1 1 SATN5 0 0 0 1 SATN4 0 0 0 1 SATN3 0 0 0 1 SATN2 0 0 0 1 SATN1 0 0 0 1 SATN0 0 1 0 1
18.2.5.11 Subaddresses A8H to AEH
Table 234 Horizontal luminance scaling increment; register set A [A8H[7:0]; A9H[7:0]] and B [D8H[7:0]; D9H[7:0]] CONTROL BITS HORIZONTAL LUMINANCE SCALING INCREMENT
1024 (theoretical) zoom 1 1024 294, lower limit defined
A [A9H[7:4]] B [D9H[7:4]] XSCY[15:12](1)
A [A9H[3:0]] B [D9H[3:0]] XSCY[11:8] 0000 0001 0011 0100 0100 1111
A [A8H[7:4]] B [D8H[7:4]] XSCY[7:4] 0000 0010 1111 0000 0000 1111
A [A8H[3:0]] B [D8H[3:0]] XSCY[3:0] 0000 0110 1111 0000 0001 1111
Scale =
0000 by 0000 0000 0000 0000 0001
Scale = data path structure
Scale = 10241023 zoom Scale = 1, equals 1024 Scale = Scale = Note
1024 1025 1024 8191
downscale downscale
1. Bits XSCY[15:13] are reserved and are set to logic 0.
2004 Jun 29
182
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
Table 235 Horizontal luminance phase offset; register set A [AAH[7:0]] and B [DAH[7:0]] HORIZONTAL LUMINANCE PHASE OFFSET Offset = 0 Offset = 132 pixel Offset = Offset =
32 32 = 1 pixel 255 pixel 32
CONTROL BITS 7 TO 0 XPHY7 0 0 0 1 XPHY6 0 0 0 1 XPHY5 0 0 1 1 XPHY4 0 0 0 1 XPHY3 0 0 0 1 XPHY2 0 0 0 1 XPHY1 0 0 0 1 XPHY0 0 1 0 1
Table 236 Horizontal chrominance scaling increment; register set A [ACH[7:0]; ADH[7:0]] and B [DCH[7:0]; DDH[7:0]] CONTROL BITS HORIZONTAL CHROMINANCE SCALING INCREMENT A [ADH[7:4]] B [DDH[7:4]] XSCC[15:12](1) This value must be set to the luminance value 12XSCY[15:0] 0000 0000 0001 Note 1. Bits XSCC[15:13] are reserved and are set to logic 0. Table 237 Horizontal chrominance phase offset; register set A [AEH[7:0]] and B [DEH[7:0]] HORIZONTAL CHROMINANCE PHASE OFFSET This value must be set to
1 XPHY[7:0] 2
A [ADH[3:0]] B [DDH[3:0]] XSCC[11:8] 0000 0000 1111
A [ACH[7:4]] B [DCH[7:4]] XSCC[7:4] 0000 0000 1111
A [ACH[3:0]] B [DCH[3:0]] XSCC[3:0] 0000 0001 1111
CONTROL BITS 7 TO 0 XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1
18.2.5.12 Subaddresses B0H to BFH
Table 238 Vertical luminance scaling increment; register set A [B0H[7:0]; B1H[7:0]] and B [E0H[7:0]; E1H[7:0]] CONTROL BITS VERTICAL LUMINANCE SCALING INCREMENT
1024 (theoretical) 1 1024 1023 zoom
A [B1H[7:4]] B [E1H[7:4]] YSCY[15:12]
A [B1H[3:0]] B [E1H[3:0]] YSCY[11:8] 0000 0011 0100 0100 1111
A [B0H[7:4]] B [E0H[7:4]] YSCY[7:4] 0000 1111 0000 0000 1111
A [B0H[3:0]] B [E0H[3:0]] YSCY[3:0] 0001 1111 0000 0001 1111
Scale = Scale = Scale = Scale =
zoom
0000 0000 0000 0000 1111
Scale = 1, equals 1024
1024 1025 downscale 1 63.999 downscale
2004 Jun 29
183
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
Table 239 Vertical chrominance scaling increment; register set A [B2H[7:0]; B3H[7:0]] and B [E2H[7:0]; E3H[7:0]] CONTROL BITS VERTICAL CHROMINANCE SCALING INCREMENT A [B3H[7:4]] B [E3H[7:4]] YSCC[15:12] This value must be set to the luminance value YSCY[15:0] 0000 1111 A [B3H[3:0]] B [E3H[3:0]] YSCC[11:8] 0000 1111 A [B2H[7:4]] B [E2H[7:4]] YSCC[7:4] 0000 1111 A [B2H[3:0]] B [E2H[3:0]] YSCC[3:0] 0001 1111
Table 240 Vertical scaling mode control; register set A [B4H[4 and 0]] and B [E4H[4 and 0]]; note 1 CONTROL BITS 4 AND 0 VERTICAL SCALING MODE CONTROL YMIR Vertical scaling performs linear interpolation between lines Vertical scaling performs higher order accumulating interpolation, better alias suppression No mirroring Lines are mirrored Note 1. X = don't care. Table 241 Vertical chrominance phase offset `00'; register set A [B8H[7:0]] and B [E8H[7:0]] VERTICAL CHROMINANCE PHASE OFFSET Offset = 0 Offset = Offset =
32 32 = 1 line 255 lines 32
YMODE 0 1 X X
X X 0 1
CONTROL BITS 7 TO 0 YPC07 0 0 1 YPC06 0 0 1 YPC05 0 1 1 YPC04 0 0 1 YPC03 0 0 1 YPC02 0 0 1 YPC01 0 0 1 YPC00 0 0 1
Table 242 Vertical luminance phase offset `00'; register set A [BCH[7:0]] and B [ECH[7:0]] VERTICAL LUMINANCE PHASE OFFSET Offset = 0 Offset = Offset =
32 32 = 1 line 255 lines 32
CONTROL BITS 7 TO 0 YPY07 0 0 1 YPY06 0 0 1 YPY05 0 1 1 YPY04 0 0 1 YPY03 0 0 1 YPY02 0 0 1 YPY01 0 0 1 YPY00 0 0 1
2004 Jun 29
184
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
19 PROGRAMMING START SET-UP OF DIGITAL VIDEO DECODER PART 19.1 Decoder part
The given values force the following behaviour of the SAA7108AE; SAA7109AE decoder part: * The analog input AI11 expects an NTSC M, PAL B, D, G, H and I or SECAM signal in CVBS format; analog anti-alias filter and AGC active * Automatic field detection enabled * Standard ITU 656 output format enabled on the expansion port * Contrast, brightness and saturation control in accordance with ITU standards * Adaptive comb filter for luminance and chrominance activated * Pins LLC, LLC2, XTOUTd, RTS0, RTS1 and RTCO are set to 3-state. Table 243 Decoder part start set-up values for the three main standards SUB ADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 VALUES (HEX) REGISTER FUNCTION chip version increment delay analog input control 1 analog input control 2 analog input control 3 analog input control 4 horizontal sync start horizontal sync stop sync control luminance control luminance brightness control luminance contrast control chrominance saturation control chrominance hue control chrominance control 1 chrominance gain control chrominance control 2 mode/delay control ID7 to ID4 X, X, X, X, IDEL3 to IDEL0 FUSE1, FUSE0, GUDL1, GUDL0 and MODE3 to MODE0 X, HLNRS, VBSL, WPOFF, HOLDG, GAFIX, GAI28 and GAI18 GAI17 to GAI10 GAI27 to GAI20 HSB7 to HSB0 HSS7 to HSS0 AUFD, FSEL, FOET, HTC1, HTC0, HPLL, VNOI1 and VNOI0 BYPS, YCOMB, LDEL, LUBW and LUFI3 to LUFI0 DBRI7 to DBRI0 DCON7 to DCON0 DSAT7 to DSAT0 HUEC7 to HUEC0 CDTO, CSTD2 to CSTD0, DCVF, FCTC, X and CCOMB ACGC and CGAIN6 to CGAIN0 OFFU1, OFFU0, OFFV1, OFFV0, CHBW and LCBW2 to LCBW0 COLO, RTP1, HDEL1, HDEL0, RTP0 and YDEL2 to YDEL0 08 C0 10 90 90 EB E0 98 40 80 44 40 00 89 2A 0E 00 BIT NAME(1) NTSC M PAL B, D, G, H AND I read only 08 C0 10 90 90 EB E0 98 40 80 44 40 00 81 2A 06 00 08 C0 10 90 90 EB E0 98 1B 80 44 40 00 D0 80 00 00 SECAM
2004 Jun 29
185
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SUB ADDRESS (HEX) 12 13 14 15 16 17 18 19 1A to 1E 1F Note
VALUES (HEX) REGISTER FUNCTION RT signal control RT/X port output control analog/ADC/compatibility control VGATE start, FID change VGATE stop miscellaneous, VGATE configuration and MSBs raw data gain control raw data offset control reserved BIT NAME(1) NTSC M RTSE13 to RTSE10 and RTSE03 to RTSE00 RTCE, XRHS, XRVS1, XRVS0, HLSEL and OFTS2 to OFTS0 CM99, UPTCV, AOSL1, AOSL0, XTOUTE, OLDSB, APCK1 and APCK0 VSTA7 to VSTA0 VSTO7 to VSTO0 LLCE, LLC2E, X, X, X, VGPS, VSTO8 and VSTA8 RAWG7 to RAWG0 RAWO7 to RAWO0 X, X, X, X, X, X, X, X 00 00 00 11 FE 40 40 80 00 PAL B, D, G, H AND I 00 00 00 11 FE 40 40 80 00 read only SECAM 00 00 00 11 FE 40 40 80 00
status byte video decoder INTL, HLVLN, FIDT, GLIMT, GLIMB, (OLDSB = 0) WIPA, COPRO and RDCAP
1. All X values must be set to logic 0.
2004 Jun 29
186
Philips Semiconductors
Product specification
HD-CODEC
19.2 Audio clock generation part
SAA7108AE; SAA7109AE
The given values force the following behaviour of the SAA7108AE; SAA7109AE audio clock generation part: * Used crystal is 24.576 MHz * Expected field frequency is 59.94 Hz (e.g. NTSC M standard) * Generated audio master clock frequency at pin AMCLK is 256 x 44.1 kHz = 11.2896 MHz * AMCLK is externally connected to AMXCLK (short-cut between pins K12 and J12) * ASCLK = 32 x 44.1 kHz = 1.4112 MHz * ALRCLK is 44.1 kHz. Table 244 Audio clock part set-up values SUB ADDRESS (HEX) 30 31 32 33 34 35 36 37 38 39 3A 3B to 3F Note 1. All X values must be set to logic 0. START VALUES REGISTER FUNCTION audio master clock cycles per field; bits 7 to 0 audio master clock cycles per field; bits 15 to 8 audio master clock cycles per field; bits 17 and 16 reserved audio master clock nominal increment; bits 7 to 0 audio master clock nominal increment; bits 15 to 8 audio master clock nominal increment; bits 21 to 16 reserved clock ratio AMXCLK to ASCLK clock ratio ASCLK to ALRCLK audio clock generator basic set-up reserved BIT NAME(1) 7 ACPF7 to ACPF0 ACPF15 to ACPF8 X, X, X, X, X, X, ACPF17 and ACPF16 X, X, X, X, X, X, X, X ACNI7 to ACNI0 ACNI15 to ACNI8 X, X, ACNI21 to ACNI16 X, X, X, X, X, X, X, X X, X, SDIV5 to SDIV0 X, X, LRDIV5 to LRDIV0 X, X, X, X, APLL, AMVR, LRPH, SCPH X, X, X, X, X, X, X, X 1 1 0 0 1 1 0 0 0 0 0 0 6 0 1 0 0 1 1 0 0 0 0 0 0 5 1 0 0 0 0 0 1 0 0 0 0 0 4 1 1 0 0 0 0 1 0 0 1 0 0 3 1 1 0 0 1 1 1 0 0 0 0 0 2 1 1 0 0 1 1 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 HEX BC DF 02 00 CD CC 3A 00 03 10 00 00
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Product specification
HD-CODEC
19.3 Data slicer and data type control part
SAA7108AE; SAA7109AE
The given values force the following behaviour of the SAA7108AE; SAA7109AE VBI data slicer part: * Closed captioning data is expected at line 21 of field 1 (60 Hz/525 line system) * All other lines are processed as active video * Sliced data are framed by ITU 656 like SAV/EAV sequence (DID[5:0] = 3EH MSB of SAV/EAV = 1). Table 245 Data slicer start set-up values SUB ADDRESS (HEX) 40 41 to 53 54 55 to 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 Notes 1. All X values must be set to logic 0. 2. Changes for 50 Hz/625 line systems: subaddress 5AH = 03H and subaddress 5BH = 03H. START VALUES REGISTER FUNCTION slicer control 1 line control register 2 to 20 line control register 21 line control register 22 to 24 programmable framing code horizontal offset for slicer vertical offset for slicer field offset and MSBs for horizontal and vertical offset reserved header and data identification code control reserved slicer status byte 0 slicer status byte 1 slicer status byte 2 BIT NAME(1) 7 X, HAM_N, FCE, HUNT_N, X, X, X, X LCRn_7 to LCRn_0 (n = 2 to 20) LCR21_7 to LCR21_0 FC7 to FC0 HOFF7 to HOFF0 VOFF7 to VOFF0 FOFF, RECODE, X, VOFF8, X, HOFF10 to HOFF8 X, X, X, X, X, X, X, X FVREF, X, DID5 to DID0 0 1 0 0 0 0 1 0 0 0 0 6 1 1 1 1 0 1 0 0 0 0 0 0 5 0 1 0 1 0 0 0 0 0 1 0 0 4 0 1 1 1 0 0 0 0 0 1 0 0 3 0 1 1 1 0 0 0 0 0 1 0 0 2 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 0 HEX 40 FF 5F FF 00 47 06(2) 83(2) 00 3E 00 00
LCRn_7 to LCRn_0 (n = 22 to 24) 1
sliced data identification code X, X, SDID5 to SDID0 X, X, X, X, X, X, X, X -, FC8V, FC7V, VPSV, PPV, CCV, -, - -, -, F21_N, LN8 to LN4 LN3 to LN0, DT3 to DT0
read-only register read-only register read-only register
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Product specification
HD-CODEC
19.4 Scaler and interfaces 19.4.1
SAA7108AE; SAA7109AE
TRIGGER CONDITION
Table 246 shows some examples for the scaler programming where: * prsc = prescale ratio * fisc = fine scale ratio * vsc = vertical scale ratio. number of input pixel The ratio is defined as: ---------------------------------------------------------number of output pixel In the following settings the VBI data slicer is inactive. To activate the VBI data slicer, VITX[1:0] 86H[7:6] has to be set to `11'. Depending on the VBI data slicer settings, the sliced VBI data is inserted after the end of the scaled video lines, if the regions of the VBI data slicer and scaler overlap. To compensate for the running-in of the vertical scaler, the vertical input window lengths are extended by 2 to 290 lines, respectively 242 lines for XS, but the scaler increment calculations are done with 288, respectively 240 lines. 19.4.3 EXAMPLES
For trigger condition STRC[1:0] 90H[1:0] not equal `00'. If the value of (YO + YS) is 262 (NTSC), and 312 (PAL) the output field rate is reduced to 30 Hz and 25 Hz respectively. Horizontal and vertical offsets (XO and YO) have to be used to adjust the displayed video in the display window. As this adjustment is application dependent, the listed values are only dummy values. 19.4.2 MAXIMUM ZOOM FACTOR
The maximum zoom factor is dependent on the back-end data rate and is therefore back-end clock and data format dependent (8 or 16-bit output). The maximum horizontal zoom is limited to approximately 3.5, due to internal data path restrictions.
Table 246 Example of configurations EXAMPLE NUMBER 1 SCALER SOURCE AND REFERENCE EVENTS analog input to 8-bit I port output, with SAV/EAV codes, 8-bit serial byte stream decoder output at X port; acquisition trigger at falling edge vertical and rising edge horizontal reference signal; H and V gates on IGPH and IGPV, IGP0 = VBI sliced data flag, IGP1 = FIFO almost full, level 24, IDQ qualifier logic 1 active INPUT OUTPUT WINDOW WINDOW SCALE RATIOS
720 x 240 720 x 240 prsc = 1; fisc = 1; vsc = 1
2
analog input to 16-bit output, without SAV/EAV codes, Y on 704 x 288 768 x 288 prsc = 1; I port, CB-CR on H port and decoder output at X port; fisc = 0.91667; acquisition trigger at falling edge vertical and rising edge vsc = 1 horizontal reference signal; H and V pulses on IGPH and IGPV, output FID on IGP0, IGP1 fixed to logic 1, IDQ qualifier logic 0 active X port input 8 bit with SAV/EAV codes, no reference signals on XRH and XRV, XCLK as gated clock; field detection and acquisition trigger on different events; acquisition triggers at rising edge vertical and rising edge horizontal; I port output 8-bit with SAV/EAV codes like example number 1; see Table 247 720 x 240 352 x 288 prsc = 2; fisc = 1.022; vsc = 0.8333
3
4
X port and H port for 16-bit Y-CB-CR 4 : 2 : 2 input (if no 16-bit 720 x 288 200 x 80 output selected); XRH and XRV as references; field detection and acquisition trigger at falling edge of vertical and rising edge of horizontal; I port output 8-bit with SAV/EAV codes, but Y only output 189
prsc = 2; fisc = 1.8; vsc = 3.6
2004 Jun 29
Philips Semiconductors
Product specification
HD-CODEC
Table 247 Scaler and interface configuration examples I2C-BUS ADDRESS (HEX) Global settings 80 83 84 85 86 87 88 task enable, IDQ and back-end clock definition XCLK output phase and X port output enable IGPH, IGPV, IGP0 and IGP1 output definition signal polarity control and I port byte swapping FIFO flag thresholds and video/text arbitration ICLK and IDQ output phase and I port enable power save control and software reset 10 01 A0 10 45 01 F0 - - - - - - - - - - - 16 - 720 - 10 - 242 - 720 - 240 - - - - 128 64 64
SAA7108AE; SAA7109AE
EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4 MAIN FUNCTION HEX DEC HEX DEC HEX DEC HEX DEC
10 01 C5 09 40 01 F0
- - - - - - - - - - - 16 - 704 - 10 - 290 - 768 - 288 - - - - 128 64 64
10 00 A0 10 45 01 F0
- - - - - - - - - - - 16 - 720 - 10 - 242 - 352 - 288 - - - - 128 64 64
10 00 A0 10 45 01 F0
- - - - - - - - - - - 16 - 720 - 10 - 290 - 200 - 80 - - - - 128 17 17
Task A: scaler input configuration and output format settings 90 91 92 93 task handling scaler input source and format definition reference signal definition at scaler input I port output formats and configuration 00 08 10 80 00 08 10 40 00 18 10 80 00 38 10 84
Input and output window definition 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F horizontal output (destination) window length (XD) vertical output (destination) window length (YD) vertical input (source) window length (YS) vertical input offset (YO) horizontal input (source) window length (XS) horizontal input offset (XO) 10 00 D0 02 0A 00 F2 00 D0 02 F0 00 10 00 C0 02 0A 00 22 01 00 03 20 01 10 00 D0 02 0A 00 F2 00 60 01 20 01 10 00 D0 02 0A 00 22 01 C8 00 50 00
Prefiltering and prescaling A0 A1 A2 A4 A5 A6 integer prescale (value `00' not allowed) accumulation length for prescaler FIR prefilter and prescaler DC normalization scaler brightness control scaler contrast control scaler saturation control 01 00 00 80 40 40 01 00 00 80 40 40 02 02 AA 80 40 40 02 03 F2 80 11 11
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Product specification
HD-CODEC
SAA7108AE; SAA7109AE
I2C-BUS ADDRESS (HEX)
EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4 MAIN FUNCTION HEX DEC HEX DEC HEX DEC HEX DEC
Horizontal phase scaling A8 A9 AA AC AD AE horizontal phase offset chrominance Vertical scaling B0 B1 B2 B3 B4 B8 to BF vertical scaling mode control vertical phase offsets luminance and chrominance (needs to be used for interlace correct scaled output) vertical scaling increment for chrominance vertical scaling increment for luminance 00 04 00 04 00 1024 - 1024 - - 00 04 00 04 00 1024 - 1024 - - 55 03 55 03 00 853 - 853 - - 66 0E 66 0E 01 3686 - 3686 - - horizontal phase offset luminance horizontal scaling increment for chrominance horizontal scaling increment for luminance 00 04 00 00 02 00 1024 - - 512 - - AA 03 00 D5 01 00 938 - - 469 - - 18 04 00 0C 02 00 1048 - - 524 - - 34 07 00 9A 03 00 1844 - - 922 - -
start with B8 to BF at 00H, if there are no problems with the interlaced scaled output optimize according to Section 9.3.3.2
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Philips Semiconductors
Product specification
HD-CODEC
20 PACKAGE OUTLINE
SAA7108AE; SAA7109AE
BGA156: plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm
D D1 B A
SOT472-1
ball A1 index area A E1 E A1 detail X A2
C e1 e P N M L K J H G F E D C B A shape optional (4x) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.75 A1 0.5 0.3 A2 1.25 1.05 b 0.6 0.4 D 15.2 14.8 D1 13.7 13.0 E 15.2 14.8 E1 13.7 13.0 e 1 e1 13 e2 13 v 0.3 w 0.1 y 0.15 y1 0.35 10 mm X
1/2 e
b
v M C A B w M C
y1 C
y
e
e2
1/2 e
OUTLINE VERSION SOT472-1
REFERENCES IEC 144E JEDEC MS-034 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 00-03-04 03-01-22
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Philips Semiconductors
Product specification
HD-CODEC
21 SOLDERING 21.1 Introduction to soldering surface mount packages
SAA7108AE; SAA7109AE
To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 21.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 21.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON-T and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 21.3 Wave soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
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Product specification
HD-CODEC
21.5
SAA7108AE; SAA7109AE
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L(8), PMFP(9), WQCCN..L(8) Notes
not suitable not suitable(4) suitable not not recommended(5)(6) recommended(7)
not suitable
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages.
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Product specification
HD-CODEC
22 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
SAA7108AE; SAA7109AE
DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 23 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 24 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Product specification
HD-CODEC
25 PURCHASE OF PHILIPS I2C COMPONENTS
SAA7108AE; SAA7109AE
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R21/02/pp197
Date of release: 2004 Jun 29
Document order number:
9397 750 13425

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